Memory dump

ABSTRACT

A DATA PROCESSING SYSTEM WHEREIN A PERIPHERAL UNIT COMMUNICATES WITH A MEMORY STORE WHILE THE CENTRAL PROCESSING UNIT CONTINUES TO EXECUTE ITS NORMAL SEQUENCE OF OPERATIONS. THE CENTRAL DATA PROCESSING UNIT RESPONDS ONLY TO THE APPROPRIATE SIGNAL TO PROVIDE THE NECESSARY DATA ITEM TRANSFER AND TO HALT THE TRANSFER THEREOF. A BUFFER REGISTER TRANSMITS OR RECEIVES DATA WORDS TO OR FROM THE PERIPHERAL DEVICE IN SUCCESSION. WHEN THE BUFFER REGISTER IS FILLED WITH THE INFORMATION FROM THE PERIPHERAL UNIT OR HAS TRANSFERRED THE INFORMATION TO THE PERIPHERAL UNIT, A SIGNAL IS TRANSMITTED TO THE CENTRAL DATA PROCESSING UNIT WHICH PROVIDES THE COMMUNICATION BETWEEN THE BUFFER REGISTER AND THE MEMORY STORE.

y 1971 H. L. HEROLD ErAL Re. 27,157

APPARATUS IN DATA PROCESSING SYSTEM FOR COORDINATING MEMORY COMMUNICATION AMONG PROCESSORS AND PERIPHERAL DEVICES Original Filed Feb. 4.2, 1960 (me/1cm? 0 r 5 R EEMEE /Z0 15 .SOATEIP' co/vm MEMO/P) u/v/r PEADEP 10 f 16 25 15 f I/ CENTRAL MULT/PLEX P Bum: PE0cE5s0E EUEEEE Fae/"m? 14 17 comma. TrPE- mp5 WRITER CONTROL cameo;

CONSOLE wwr -1 1 1a 19 F f f i 1 TAPE TAPE i HANDLER HANDLER I l i INVENTORJ' ATTORW United States Patent APPARATUS IN DATA PROCESSING SYSTEM FOR COORDINATING MEMORY COMMUNICATION AMONG PROCESSORS AND PERIPHERAL DE- VICES Henry L. Herold, Los Angeles, Calif., and Joseph Weizenbaum, Concord, Mass., assignors to Honeywell Information Systems Inc.

Original No. 3,354,466, dated Nov. 21, 1967, Ser. No. 8,394, Feb. 12, 1960. Application for reissue Ian. 13, 1969, Ser. No. 801,872

Int. Cl. G06f 3/00 U.S. Cl. 340-1725 39 Claims Matter enclosed in heavy brackets appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.

ABSTRACT OF THE DISCLOSURE A data processing system wherein a peripheral unit communicates with a memory store while the central processing unit continues to execute its normal sequence of operations. The central data processing unit responds only to the appropriate signal to provide the necessary data item transfer and to halt the transfer thereof. A bufier register transmits or receives data words to or from the peripheral device in succession. When the buffer register is filled with the information from the peripheral unit or has transferred the information to the peripheral unit, a signal is transmitted to the central data processing unit which provides the communication between the bufier register and the memory store.

[TOPICS Column General Descri tion. 3 Descri tion of rawings 5 Data rocessing System-General 7 Date Representation 8 Iliod-Bits- System Circuit Elements 14 Clock Pulse Generator 14 Clock Pulse Drivcr 16 Fli Flop 17 A D-Gatc. 0 OR-Gatc. 2!

In verter 22 Emitter Follower 22 Register Transfer 28 One-Shot .95 Register.... 26 Data Processing System-Details 27 Data Processing Onrrations- 29 Glossary and Index of Signals 89 Definitions... 60 Component Details and Operations 61 The Logical Schematic Diagram 51 Central Processor 64 Timing Circuit- 70 Clock Circuit 72 J-Mod-Gcnerntor 78 Arithmetic Unit. 7,; Control Console-.- 78 Clear Controls 7'8 Starting Controls 79 Ilalt Controls 80 Sequential Memory Location Operation Controls 80 Miscellaneous Switches 81 Memory 81 Core Memory. 82

Data Storage 88 Core Memory Addressing: Store and Road Out 85 "ice Re. 27,157 Reissueci July 20, 1971 TOPICS-Continued Column Core Memory Data Read Out 88 M-Register 89 General Operation and Timing 91 Control Circuit 9i P-Buticr 9.? Clock Circuit, P-Butier 95 P M rid-Gen orator 95 Control Typewriter 96 Data Input. from Control Typewriter 96 Data Out ut to Control Typewriter- 97 Register ype-in 98 Register Type-Out- 98 Central Processor Control. 99 100 I00 100 Clock Circuit. Write Builer 108 Tape Handler 04 Tape Control Unit- 107 Read Buflcr H1 Clock Circuit, Read Buiier It Prin .r 114 Sorter and Character Reader. 114 Sorter Control Unit 118 Clock Circuit, Sorter Control Unit- I21 Instructions 121 Initial Routine During Instruction- 122 Memory Cycle 122 Details or Initial Routine. I2! Module-3 Check 128 instruction 2i: Exchange R and M (XRM) 1% Instruction 'lransier R to M (TRM), 126 Instruction 'lrnnsicr M to R (TMR) I26 Instruction Transfer M to FULL (TMF). 127 Instruction 30 'ironsler FULL to M (TFM). 188 Instruction 94 Exchange R and I! (XRB) 128 Instruction 97: Exchange L and R (XLRL- 129 Instruction Shift R Right (N) (SHE).-- 180 Instruction 91: Ring Shift R (N) (RBR).- 130 Instruction 92:

Shift FULL Right (N) (SITF) 131 Analysis ofJnint Use of A and W to Control Shift Count-- 133 Instruction 93'. Ring Shift FULL (N) (RSF) 134 Instruction 25: Mod-3 Generation on R (GM R) 134 instruction '26: Mod-3 Generation on L and R (GMF)- 135 Instruction 53: Halt (HLI) 136 Instruction 63: Jump Uncondiiionnlly (J UN) 137 Instruction 61: Jump Uncondilionally, "lransier N to I! (JNH). 157 Instruction 60:

Branch ii Dl (BDl) 138 Halt O tlnn 138 Instruction 62: llrench if D2 (BD2) I89 Instruction 64: Branch ii D3 (BDB) I89 Instruction 54: Does Condition X Exist? (DSW) 140 Instruction 50: Change State of Sign or Dosignntor or R, or

Change Jc (CHR) 1M Instruction 76: Is R Greater Than M 7 (RGM) 4 Instruction 86: Is L-R Greater Than MA and hIri-l'l (FGM)-.- instruction 3 R Une ual to M? (RUM) 4 Instructinn $11: Is L-R inequnl to M; and M +lT (FUM). 46 Instruction 31:

Find Word in Memory Equal to 12-)? (FND)- 4 Halt Search or Tumble Variation 4 Instruction 36:

Find Word in Memory Equal to or Greater Than FULL FOR 149 Halt Search or Tumble Variat 160 Instruction 35:

Tumble ('lUM) 150 Halt Search or Tumble Variation 15g Instruction 72:

Add M to R (AMR) 152 Mathematical Analysis oi Results of Complemcnlatiom. 154 Mndulo-3 Comparison 1,55 Instruction 73: Subtract M From R (BM R) 15 Instruction 82:

. I67 I62 I62 163 164 164 166 Instruction 29: Extract M Into R by L (EXT) 166 Instruction 42:

Multiply M by R (MPY) 'Iz Snbsequence 163 TOPICS-Continued Column Td Euhseouence 188 Miscellaneous Logic Relationships 169 Tape Interrupt Variation Not Necessary 170 Mod-Check 170 Mathematical Analysis of the subtractive 'lri Subsequence 170 Instruction 43:

Divide FULL by M (DIVi. 174 Miscellaneous Logic Relationships 176 Tape Interrupt Variation Not Necessary. 176 Mod-Check 1T6 Instruction 65:

Read Magnetic Tape or Character Reader (EMT) 180 Magnetic Tape Reading 180 Character Reading 183 Instruction 66:

Write Magnetic Tape or Load Printer (WMT) 188 Magnetic Tape Writing 188 Printer Writing 35 Instruction 68: Write Bloclrettes on Magnetic Tape or Loud Printer (WMB) 185 Instruction 51: Alter Magnetic Tape (AMT)... 186 Instruction 58: Start or Stop Check Feeding (CII 187' Instruction 57: Select Sorter Pocket (N) (POC)- 188 Instruction 24: Transfer I to M (TPM) 189 Instruction 74: Transfer M to I (TMP) 190 Ins}t rIuction 59: Photoreader or Control Typewriter In or Out 191 Instruction 52: Ring Bell or Gong (BNO). 192 A ntornatic Subroutines 192 Ii -Suhroutine I93 Designntor Bit Suhrontine- 194 Augmentor Bit Subroutine i9, Breakpoint Bit Subroutlnc 195 al 195 Manual Walt 196 196 Address I-Ialt 196 Alarm Halt 196 Alarms.-. 1,96 Sub-Alarms 197 Full Alarms 197 Operations From Holt Mode 199 Original Insertion of Instructions and Operands in Memory- 199 Starting System From Halt Mode 199 Sinelc-Cy gm Zingie-Cycie 200 Recycle 02 Mannally-0ontrolled Operations Involving Sequential Memory Locations 20,9 Count-Up of Instruction Address Portion 903 Control Typewriter Load Memory Operation 904 Photnreaiier Load Memory Operation 205 Dump Memory Operation 2 (cunt-Up Recycle Operation 207 P-Iluii'cr Operations- 207 Transfer of P-Reglster Contents to M-Rezister- 08 Transfer of M-Register Contents to P-Registor 208 Control Typewriter Input to P-Register Single Numeric or First Half Double-Precision Word e09 Module-8 Generation for Numeric Inputs to P-Registen- 13 Parity Checking 14 Photoreadcr Input to P-Register; Single Numeric or First Half Double-Precision Word 215 Control Typewriter or Photoreader Input to P-Registcr;

Second Half Douhle-Precision Word 21 Control Typewriter or Photoreader Input to P-Registcr:

Alphanumeric Word g1; hree Alphanumeric Characters Entered. 219 Less Than Three Alphanumeric Characters Enicred. 220 Control 'Iy writer Output from P-Ilegisier; Single Numeric or First all Double-Precision Word 20 Parity Bit Generation 224 Control Typewriter Output from P-Ilegister Second Hail Double-Precision Word 226 Control Typewriter Output from P-Reglster Alphanumeric Word 2.96 Register Type-Out Register Type-In; General 2,97 Register TypeOut 9; Register Type- 229 Multiplex Ilnilcr Opt-rations 331 Write liuiicr Operations g3; Write Program-Interrupt Operation :3 Write Instruction-Parallel Operation 33 Write instruction-Interrupt O eration 3 Illoclrclle Variation of Write ufier Operations 33 Write Butler Data Trrmsler for Magnetic Tape Writing 2 0 Write Butler Data Transfer for Printer 9 3 Rtfld Buffer Operations 244 Read Program-Interrupt Operotiom- 345 Read Instruction-Parallel Operatiom- Iicarl Instruction-Interrupt Operation 2 Read liuiier Data Tronsler for Magnetic Tape Reading" 948 Data Retiming Dur ng Magnetic Tape Reading 3 Read Butler Data Transfer [or Document Reading 255 Document Reading and Sorting 3 Document Reading Operation 259 TABLES 0F FREQUENT REFERENCE Sumner Column Digit Configurations 9 Data Word Configuration 9 Instruction Word Configuration 0 Alphanumeric Word Configuration. 10 Alphanumeric Character Code- 4 Register Flip-Flop Identification 27 Control Typewriter Two-Digit Character Codes.. 87 Sorter Control Unit Digits. 119 Interrogations 40 P-Buiier Operations 11 Multiplex Butler Operations During Instructions 884] 4 GENERAL DESCRIPTION This invention relates to information processing apparatus and more particularly to apparatus for processing data at high speeds and adapted to communicate with slower operating components.

In the processing of data, various arithmetic and logical operations are performed on data items by a data processing unit, which is adapted to execute a sequence of these operations in a very short period of time. To maintain a rapid rate of execution of these operations, the data processing unit must be able to immediately receive data items when needed and to immediately store data items after processing. Rapid receipt and storage of data items by the data processing units is provided by a high-speed random access memory. The random access memory operates at a rate of speed compatible with that of the data processing unit and rapidly supplies a data item needed by the data processing unit or rapidly stores a data item provided by the data processing unit.

From time to time, the data processing unit will complete the processing of the data items in the memory or will fill the available memory storage space with processed data items, so that means must be provided to supply the memory with new data items for processing or to empty the memory contents into another storage medium. Consequently, additional storage media are provided, such as magnetic tape data storage units. These magnetic tape units communicate with the memory, under control of the data processing unit, to transmit new data items to the memory or to receive processed data items therefrom. However, magnetic tape units transmit and receive data items at a much slower rate than the data processing unit processes data; that is, the time between transmittal or receipt of successive data items by a tape unit is comparable to the time required for the data processing unit to execute several operations. Therefore, it is desirable, in order to maintain a high average data processing speed, that the data processsing unit does not remain idle during a period when the magnetic tape unit is filling or unloading the memory. Instead, it is preferable that the data processing unit continue to execute the aforementioned sequence of operations, pausing only when the magnetic tape unit is ready to receive from or transmit to the memory a complete data item.

Therefore, it is an object of this invention to provide a high-speed data processing system adapted to communicate with slower operating components.

Another object of this invention is to provide a data processing system adapted to operate with minimum time of interruption for communication with slower operating components.

Another object of this invention is to provide a data processing system adapted to communicate with a slower operating component by halting only when a complete data item is ready to be transmitted or received by said component.

The foregoing objects are achieved by providing a data processing system wherein appropriate signals are delivcred when a mangetic tape unit is ready to receive from or transmit to the memory a complete data item and wherein the data processing unit of said system continues to execute its normal sequence of operations, responding only to these signals to provide the necessary data item transfer. A first register is adapted to receive new data items from a magnetic tape unit and a second register is adapted to transmit processed data items to another magnetic tape unit. A first signal issues when the first register has a complete data item therein to notify the data processing unit that this data item must be transferred to the memory. A second signal issues when the second register is ready to receive a complete data item to notify the data processing unit that another data item must be transferred from the memory to the second register. In response to either one of these two signals, the data processing unit will effect the required data item transfer between the memory and one of these registers. This transfer will take place during a period wherein no data item is to be transferred between the data processing unit and the memory. The data processing unit is adapted to discontinue executing its sequence of operations in response to either one of these signals in order to provide a period of sufficient duration to effect the required data item transfer.

In a data processing unit of the type described, the random access memory frequently stores a plurality of data items distinguishable from each other by an identifying number. For example, the memory may contain credit and debit items for a plurality of accounts, wherein each credit and debit item in the memory is provided with a corresponding account number. In order to provide expeditious processing of such credit and debit items, it is convenient to store these items in sequential memory locations in accordance with the numerical order of their associated account numbers. In sorting such account numbers into numerical order it is often necessary to determine the proper memory location for insertion of an unsorted number among a sequence of sorted numbers, and then to insert the unsorted number in this memory location among the sorted numbers.

It is, therefore, another object of this invention to provide a novel data processing system for sorting data items.

Another object of this invention is to provide apparatus for the rapid sorting of data items.

Another object of this invention is to provide apparatus for the sorting of data items according to the numerical content thereof.

Another object of this invention is to provide apparatus for sorting by insertion of unsorted data items among a sorted sequence of data items.

The immediately preceding objects are achieved by providing for the insertion of the unsorted data item into its proper sequential memory location among the sorted data items and by shifting the supplanted data item and the data items following in the sorted group to their next successive memory locations to accommodate the new entry. A register is provided for holding the unsorted data item to be inserted in the memory. An addressing means provides a sequence of memory location addresses starting from the memory location wherein the unsorted data item is to be stored. In response to each address of such sequence, the contents of the register and the addressed memory location are exchanged. When a data item having a predetermined configuration in the least significant digit position thereof is transferred to the register, a signal issues. In response to this signal further exchanges are discontinued.

DESCRIPTION OF THE DRAWINGS The invention will be described with reference to the accompanying drawings, wherein:

FIGURE 1 is a block diagram of a data processing system to which the instant invention is applicable;

[FIGURE 2 is a circuit diagram of a clock pulse generator useful in the system of FIG. 1;

FIGURE 3 is a circuit diagram of a clock pulse driver useful in the system of FIG. 1, and illustrates two symbols employed to represent the clock pulse driver;

FIGURE 4 is a circuit diagram of a flip-flop useful in the system of FIG. 1, and illustrates a symbol employed to represent the flip-flop;

FIGURE 5 is a circuit diagram of an AND-gate useful in the system of FIG. 1, and illustrates a symbol employed to represent the AND-gate;

FIGURE 6 is a circuit diagram of an OR-gate useful in the system of FIG. 1, and illustrates a symbol employed to represent the OR-gate;

FIGURE 7 is a circuit diagram of an inverter useful in the system of FIG. 1, and illustrates a symbol employed to represent the inverter;

FIGURE 8 provides circuit diagrams of two emitter followers useful in the system of FIG. 1, and illustrates the symbol employed to represent an emitter follower;

FIGURE 9 is a circuit diagram of a register transfer circuit useful in the system of FIG. 1, and illustrates a symbol employed to represent the register transfer;

FIGURE 10 is a circuit diagram of a register transfer interconnecting a pair of flip-flops;

FIGURE 11 is a circuit diagram of a one-shot useful in the system of FIG. 1, and illustrates a symbol employed to represent the one-shot;

FIGURE 12 is a block diagram of the data storage elements, the data transfer paths between these elements, and the major control elements of the system of FIG. 1;

FIGURE 13 is a block diagram of the circuits providing the input signals to a flip-flop of the system;

FIGURES 14a, 14b, and 14c provide a block diagram of the Central Processor of the system;

FIGURE 15 is a timing diagram illustrating the timing sequence of the Central Processor;

FIGURE 16 is a block diagram of the circuits providing the input signals to the T-counter of the Central Processor;

FIGURE 17 is a block diagram of the clock circuit of the Central Processor;

FIGURE 18 is a block diagram of the Arithmetic Unit of the Central Processor;

FIGURES 19a and 19b provide a circuit diagram of the Control Console of the system;

FIGURE 20 is a block diagram of the Memory of the system;

FIGURE 21 illustrates a magnetic core employed in the Memory of FIG. 20;

FIGURE 22 is a graph illustrating the hysteresis loop of the magnetic core of FIG. 22;

FIGURE 23 is a circuit diagram of an inhibit driver useful in the Memory;

FIGURE 24 is a block diagram of a memory addressing circuit useful in the Memory;

FIGURE 24a is a circuit diagram of a' switch core driver useful in the memory addressing circuit of FIG. 24;

FIGURE 25 is a circuit diagram of a core read amplifier useful in the Memory;

FIGURE 26 is a circuit diagram of a strobe driver useful in the Memory;

FIGURE 27 illustrates waveforms useful in explaining the operation of the Memory;

FIGURE 28 is a block diagram of a memory control circuit useful in the Memory;

FIGURE 29 is a block diagram of the P-Buffer of the system of FIG. 1;

FIGURES 30 and 31 illustrate waveforms useful in explaining the operation of the P-Bufier;

FIGURE 32 is a block diagram of the Write Buffer employed in the Multiplex Buffer of the system of FIG. 1

FIGURE 33 is a block diagram of the clock circuit of the Multiplex Buffer and Tape Control Unit;

FIGURES 34 and 35 are schematic diagrams illustrating the scheme for writing data on the magnetic tape of the Tape Handlers;

FIGURE 36 is a circuit diagram of a write driver useful in the Tape Control Unit;

FIGURE 37 is a block diagram of the amplifiers employed in reading data from the magnetic tape of the Tape Handlers;

FIGURE 38 is a circuit diagram of a read preamplifier useful in the Tape Handlers;

FIGURE 39 is a circuit diagram of a read amplifier useful in the Tape Control Unit;

FIGURE 40 is a block diagram of the Read Buffer employed in the Multiplex Buffer of the system of FIG. I;

FIGURE 41 is a block diZgram of the circuits providing retiming for the data read from a magnetic tape;

FIGURE 41a illustrates waveforms useful in explaining the operation of the data retiming circuits shown in FIG. 41;

FIGURE 42 is a schematic diagram of the Sorter and Character Reader of the system;

FIGURE 43 is a block diagram of the Sorter Control Unit of the system;

FIGURE 44 is a circuit diagram of interconnected amplifiers employed in the Sorter Control Unit and the Sorter;

FIGURE 45 illustrates a document adapted to be read by the Character Reader;

FIGURES 46 and 47 illustrate waveforms useful in explaining the operation of the Sorter and Sorter Control Unit;

FIGURES 48-105 illustrate logical schematic diagrams of the logical circuits providing input signals to the flipfiops of the Central Processor;

FIGURE 106 illustrates logical schematic diagrams of the logical circuits providing input signals to the oneshots of the Central Processor;

FIGURES 1070, 107b, 107c and 107d illustrate logical schematic diagrams of the logical circuits providing designated logical combination signals in the Central Processor;

FIGURES 108a and 108b illustrate logical schematic diagrams of the logical circuits providing clock pulse driver gating signals in the Central Processor;

FIGURES 109a and illustrate logical schematic diagrams of the logical circuits providing inverter signals in the Central Processor;

FIGURES 110-120 illustrate logical schematic diagrams of the logical circuits providing input signals to the flip-flops of the Memory;

FIGURES 121a, 121b, 1210 and 121d illustrate logical schematic diagrams of logical circuits in the Memory;

FIGURES 122-135 illustrate logical schematic diagrams of the logical circuits providing input signals to the flipfiops of the P-Bufier;

FIGURES 136 and 137 illustrate logical schematic diagrams of the logical circuits providing input signals to the one-shots of the P-Buffer;

FIGURES 138a and 13% illustrate logical schematic diagrams of the logical signals providing designated logical combination signals, clock pulse driver gating signals, and inverter signals in the P-Bufier;

FIGURES 139-156 illustrate logical schematic diagrams of the logical circuits providing input signals to the flip-flops of the Write Buffer;

FIGURE 157 illustrates logical schematic diagrams of the logical circuits providing input signals to flip-flops of the Tape Control Unit;

FIGURE 158 illustrates logical schematic diagrams of the logical circuits providing designated logical combination signals and clock pulse driver gating signals in the Write Buffer;

FIGURES 159-177 illustrate logical schematic diagrams of the logical circuits providing input signals to the flip-flops of the Read Buffer;

8 FIGURES 178-181 illustrate logical schematic diagrams of the logical circuits providing input signals to fiip-fiops of the Tape Control Unit;

FIGURE 182 illustrates logical schematic diagrams of the logical circuits providing input signals to the oneshots of the Read Buffer;

FIGURE 183 illustrates logical schematic diagrams of the logical circuits providing designated logical combination signals and clock pulse driver gating signals in the Read Buffer;

FIGURES 184 and 185 illustrate logical schematic diagrams of the logical circuits providing input signals to the flip-flops of the Sorter Control Unit;

FIGURE 186 illustrates logical schematic diagrams of the logical circuits providing input signals to the oneshots of the Sorter Control Unit;

FIGURE 187 illustrates logical schematic diagrams of the logical circuits providing designated logical combination signals and inverter signals in the Sorter Control Unit;

FIGURES 188-197, 198a, 198b, 199a, 199b, 200-224, 225a, 225b, 226a, 226b, 227, 228, 229a, 229b, 230a, 230b, and 231-236 are timing diagrams useful in explaining the operation of the system in executing the programmable commands;

FIGURE 237 is a timing diagram useful in explaining the operation of the system in executing the Initial Routine portion of a programmable command;

FIGURE 238 is a timing diagram useful in explaining the operation of the system in executing the B-subroutine;

FIGURES 239-241, 242a, 242b, 242e, and 243-245 are timing diagrams useful in explaining the operation of the system in executing operations employing the Multiplex Buffer] DATA PROCESSING SYSTEMGENERAL The Data Processing System of FIG. 1 is adapted to process data under operational control of a Central Processor 10. The lines interconnecting the various components illustrated in FIG. 1 represent symbolically paths of data and control communication.

The Central Processor responds to a plurality of distinct instructions which are supplied thereto in the scquential order necessary to perform a particular data processing operation. A Control Console 11 provides an indicating and control station for the operator, whereby he has access to the system for modification of the order of execution of the instructions or for data revision.

A Memory 12 stores data words which are to be processed, data words which are the results of processing, and instruction words. The Central Processor communicates with the Memory to receive therefrom data words on which operations are to be performed and instruction words, Following certain data processing operations, the Central Processor transmits the resulting data words to the Memory for storage.

A P-Bufler 13, controlled by the Central Processor, temporarily stores data words being transferred from a Control Typewriter 14 or a Photoreader 15 to Memory and data words being transferred from Memory to the Control Typewriter. The Control Typewriter receives data words from the P-Bufier and types a visible representation of these words or punches on paper tape an encoded representation of these words. The Control Typewriter also transfers data words to the P-Bufier by reading encoded punched paper tape or upon depression of Control Typewriter keys in proper sequence. The Photoreader photoelectrically reads punched encoded paper tapes and transfers the electrical representations of the data thereon to the P-Buifer.

A Multiplex Buffer 16, indirectly controlled by the Central Processor, temporarily stores data being transferred from magnetic tape or from magnetically imprinted documents to Memory and data being transferred from Memory for recording on magnetic tape or for imprinting in visible representation. A Tape Control Unit 17 directs one of a plurality of Tape Handlers 18, 19, etc., to read data from the respective magnetic tape thereof and to deliver this data to the Multiplex Buffer. The Tape Control Unit also directs one of the Tape Handlers to write data provided by the Multiplex Buffer on the respective magnetic tape thereof.

A Sorter Control Unit 20 controls the reading of data borne by documents, such as bank checks, and directs the sorting of these documents into pockets of a Sorter 21.

A Character Reader 22 senses magnetically imprinted information on these documents and delivers an encoded representation of this data to the Multiplex Buffer. The Central Processor delivers to the Sorter Control Unit data representing the pockets of Sorter 21 in order that the documents handled thereby may be appropriately sorted in accordance with the information thereon.

A printer 23 receives data words from the Multiplex Buffer and prints a visible representation of these words.

Thus, the system of FIG. 1 processes data received from magnetic tape, documents, the Control Typewriter, or the Photoreader and communicates the results of the data processing by providing a visible record, by permanently storing the results on magnetic tape, by punching paper tape, or by sorting documents.

For a complete description of the system of FIGURE 1 and of the instant invention which is embodied in such system, reference is made to United States Patent 3,077,984 issued to R. R. Johnson and assigned to the assignee of the present invention. More particularly, attention is directed to FIGURES 2 through 245 of the drawings; column 1, lines 8-73; column 2; column 3, lines 1-27; column 4, lines 55-75; columns 5 and 6; column 7, lines 1-16; column 8, lines 8-75; columns 9-258; and column 259, lines 1-35 of United States Patent 3,077,- 984, which are incorporated herein by reference and made a part of the instant patent application as if fully set forth herein.

[Data Representation The Data Processing System of FIG. 1 is adapted to process data represented by the binary code. In the binary code each element of information, termed a bit, is represented by either a 1 or a 0. In the instant system a l is represented by a positive electrical signal and a 0 by a negative electrical signal. The fundamental unit of data for processing and communication is the data word. The data Word comprises 2 8 bits.

The 28 bits of the data word are normally processed as 7 sequential groups of 4 bits. Each group is termed a digit." The bits of a digit are processed simultaneously. The grouping of the bits permits the system to perform operations in the decimal number system. The 4 bits of a group may be treated as a decimal numeral and such a group is termed a binary-coded decimal digit. Each bit of a digit corresponds to a different decimal numeral if the group is employed as a decimal digit representation. In this system, the 5-4-2-1 code is employed. The most significant bit of the digit represents the decimal 5, the next lower order bit represents the decimal 4, the next lower order bit represents the decimal 2 and the least significant bit represents the decimal 1. For example, the decimal 8 is represented by the binary bit group 1011.

Inasmuch as but 10 of the 16 possible configurations of the 4 bits of a group are employed to represent the 10 decimal numerals, 6 configurations of the group are available for other representations. The bit configurations representing the 10 decimal numerals are termed numeric" digits. Five of the remaining 6 configurations represent respectively the dollar sign (5), the comma the ampersand (8a), the period and the asterisk The remaining bit configuration, 1111, is not employed to represent data, but instead is forbidden, and is useful for detecting data processing errors. These 6 configurations representing non-numerals are termed non-numeric" digits. The 16 configurations of the binary code of a single digit or group and the corresponding symbols which they usually represent are given in the following Table I. In this table, the bits of each group are shown in decreasing order of significance.

TABLE I Symbol Single digit code - 2" enwoc-zotemac-aroi-c 1110 forbidden 1 symbols of Table I. The 7t h, or MSD, is not usually so interpreted.

This 7th digit of the data word, which is termed the condition" digit, comprises three independent representations. The most significant bit of the condition digit is termed the designator bit and is employed for automatic address modification. The next lower order bit of the condition digit is termed the sign" bit and is employed to denote the algebraic significance of the 6 least significant digits of the data word. When the sign bit is l, the data word is considered negative. When the sign bit is 0, the data word is positive. The two least significant bits of the condition digit are termed the mod-bits." The mod-bits provide a representation of the modulo-3 of the data word and are employed to check the correctness of the data word following a data transfer, or to check the correctness of an arithmetic operation employing the data word. The data word may be represented as follows:

DATA WORD Condition digit 6th th 4th 3rd 2nd 1st digit digit digit digit digit digit Designator bit 5-bit B-bit fi-bit. fi-bit 5-bit. fi-bit. Sign bit 4-bit 4-bit. 4-bit. 4-bit 4-bit. 4-bit. Mod-bit 2-bit 2-bit. 2-bit. 2-bit. 2-bit. 2-bit. Mad-bit l-bit. l-bit. l-bit. i-bit. l-bit. i-bit.

X X10 x10 x10 x10. 110.

to direct a distinct operation of the system. The instruction word is generally employed in two portions to direct an operation. The four least significant digits comprise a Memory address and denote a location in Memory where a data word is to be obtained for processing, or v where a processed word is to be stored. The next two digits comprise a command (order) code. The command code is a two decimal digit code which determines the type of operation that the system will execute.

Since the addressable locations in Memory are only 0000-3999, the 4 and 5-bit positions of the 4th digit are not needed for a Memory address. Therefore, in an instruction word, the two most significant bits of the 4th digit are employed for separate functions. The most significant bit of the 4th digit is termed the augmentor bit and is employed for automatic modification of the contents of the Memory location addressed. The next lower order bit is termed the breakpoint" bit and is employed to force the system to halt if a predetermined condition exists in the Control Console. The instruction word may be represented as follows:

The four other types of data words are those on which data processing operations are performed. Such words are generally known as operand words. The four types of operand words are: (a) Single numeric, (b) First half double-precision, (0) Second half double-precision, and (d) Alphanumeric. The single numeric word is the simple data word, described previously, and is processed in conventional manner. Each of the 6 least significant digits of the single numeric word are processed as separate entities and represents one of the 15 symbols of Table I.

A double-precision word comprises two single numeric words which are processed together. In processing the double-precision word, the numeric portions (6 least significant digits) of the two words thereof are processed as a single 12 digit number. The first half double-precision word supplies the 6 most significant digits of the 12 digit number and is termed the most significant half word (MSH). The second half double-precision word supplies the 6 least significant digits of the 12 digit number and is termed the least significant half word (LSH) Each half word of the double-precision word carries its own mod-bits, but both half words have the same designator and sign bit configurations.

The alphanumeric word is employed to represent alphabetic symbols, numerics, non-numerics, and certain special characters. In the alphanumeric word and the 6 least significant digits are paired to represent three alphanumeric characters. The alphanumeric word may be represented as follows:

ALPHANUME RIC WORD The two mod-bits of an alphanumeric word are always equal to 1,1 thereby serving to distinguish alphanumeric words from the other four types of data words.

The alphanumeric characters and the single digit code representations of the corresponding digit pairs are given in the following Table II.

TABLE II Alphanumeric Twodiglt Alphanumeric Two-digit character code characte code 6: (Mr Shift Case 2. t 0' A II V 35 ll 12 W 36 E 15 Z 30 I" 16 (l 17 Tab 33 It 18 Stop 36:

1 19 Normal Case 3.

Space Carriage Return Ignore 1dr End of Information 1,

For example, the alphanumeric code for the alphabetic Word CAT is 131133. The alphanumeric code for the number 123 is 010203, whereas the numeric portion of a single numeric data word representing the number 123 is 000123.

The special characters listed in Table II are employed to direct operations of the Control Typewriter.

The Memory may contain at any location any one of the five types of data words. However, it is general practice to store the MSH of a double-precision word in an even-numbered Memory location and the LSH of the same double-precision word in the next higher odd-numbered location.

Mod-Bits Although the configurations of the 6 least significant digits and the designator and sign bits of all data words inserted into Memory from magnetic tape, the Control Typewriter, or the Photoreader are discretionary with the operator, the configuration of the mod-bits is mandatory. The mod-bits of all words are representative of the modulo-3 thereof. The modulo-3 of a number is the remainder when that number is divided by 3. Thus, for example, the modulo-3 of 0, 3, 6, and 9, is O; of l, 4, and 7 is l (-2); and of 2. 5, and 8 is 2 (-1).

The mod-bits are employed in three different forms:

(a) The mod-bits of a numeric word in Memory and, consequently, of a word transferred between the components of the system, have the configuration required to make the modulo-3 of the entire 7 digits of the word equal to I. In determining the modulo-3 of the entire word, the designator and sign bits are assigned their respective positional values of 5 and 4. The most significant mod-bit is assigned the value of 2 and the least significant mod-bit the value of 1. Thus, the three configurations of the mod-bits (most significant bit first) are 0, 0; 0, l; and l, 0 to represent the respective numbers 0, l and 2. When a data word is transferred into the Central Processor from Memory, its correctness is tested by a mod-check," wherein the total modulo-3 of all 7 digits is accumulated. If this accumulated total is not 1, an alarm occurs and the Central Processor halts.

The employment of a total modulo-3 of l for words transferred from Memory to the Central Processor always permits a positive check on the correctness of the entire word transferred. This positive mod-check is to be contrasted with the false mod-check which would occur if the total word modulo-3 had been set, instead, to 0, and a complete failure of data transfer had occurred,

14 since a word consisting solely of 0's has a total modulo- 3 of 0.

(b) The mod-bits of an operand employed in an arithmetic operation in the Central Processor have the configuration of the total modulo-3 of the 6 least significant digits (numeric portion) of the word. Thus, in words employed for arithmetic operations with numeric portions having total modulo-Ss of 0, 1 or 2, the respective mod-bits are 0, 0; 0, l; and 1, 0. For example, when two numeric words are added the sum of the modulo- 3s thereof must be equal to the modulo-3 of the sum. Therefore, the modulo-3 of the sum is compared with the sum of the modulo-3 of the two words added. If this "mod-comparison" fails, an alarm occurs and the Central Processor halts.

(c) An alphanumeric word has no numeric portion and, therefore. no modulo-3. The mod-bits of such a word are set to the l, l configuration and serve to identify the associated data word as an alphanumeric word.

SYSTEM CIRCUIT ELEMENTS Circuits useful as elements of the system of FIG. 1 will now be described. The system will function with these elements or with other similar elements well-known in the art; therefore, this invention is not to be considered as limited to the employment of the specific circuits shown.

The following circuits find general employment in the system: clock pulse generator, clock pulse driver. flipfiop, AND gate. OR-gate. inverter, emitter follower, register transfer. and one-shot. Illustrated with the respective drawings of the circuit elements are symbols representative thereof. These symbols will be employed for simplicity in the description of the invention to follow.

In the figures for the circuit elements, specific values of the circuit components are shown. These values are not to be considered as limiting, and the circuit elements will often function satisfactorily with considerable variation from the values provided.

Clock Pulse Generator The clock pulse generator of FIG. 2 provides synchronizing signals for clock pulse drivers located throughout the system. The synchronizing signals are provided at a repetition rate of 250 kc. The clock pulse generator comprises the following four circuits connected in tandem: an oscillator, a feedback amplifier, a regenerative comparator, and an output amplifier.

The oscillator comprises a transistor 31 coupled to a resonant circuit comprising an inductor 32 and a capacitor 33. The approximate frequency of oscillation is determined by the resonant frequency of inductor 32 and capacitor 33. A crystal 34, coupled to the resonant circuit, locks the oscillator at the desired frequency. The sine wave output signal of the oscillator is taken from the emitter electrode 35 of transistor 31.

The output signal of the oscillator is transmitted through a capacitor 36 and a resistor 37 to the base electrode of transistor 38 of the feedback amplifier. The feedback amplifier has substantial voltage gain, whereby the output signal thereof, delivered at collector electrode 39, is a sine wave having an amplitude of approximately 1 volt peak-to-peak.

The output signal of the feedback amplifier is applied directly to the base electrode of transistor 45 of the regenerative comparator. The regenerative comparator is a bistable circuit delivering a substantially square wave in response to the received sine wave, and is provided for obtaining a waveform with a steep wavefront from the input signal. The regenerative comparator operates substantially as follows: Consider the portion of the cycle of operation when the input signal is negative with respect to ground, but is increasing positively. At this time transistor 45 is non-conducting and transistor 46 is conducting. In this stable state, the base electrode of transistor 46 is at 0 volt (v.), or ground.

The collector electrode of transistor 45 is at +8 v., and capacitor 47 is charged to +8 v. The emitters of both of transistors 45 and 46 will be a fraction of a volt negative with respect to ground, since transistor 46 is conducting. As the input voltage applied to the collector electrode of transistor 45 increases positively and reaches v., the emitter-base junction of transistor 45 becomes forward biased and collector current commences to tlow therein. A sharp regenerative action thereupon ensues, with transistor 45 turning on sharply and transistor 46 turning off sharply. During this regenerative action, the negative swing at the collector electrode of transistor 45 is coupled through capacitor 47 to the base electrode of transistor 46. As the emitter current of transistor 46 decreases, the emitter voltage thereof becomes more negative, increasing the forward bias of transistor 45 and sustaining the regenerative action. The time constant of capacitor 47, inductor 48 and resistor 49 is adjusted so that the sharp negative pulse at the base electrode of transistor 46 terminates in about 2 microseconds (usecs).

So long as the input signal now remains positive, transistor 45 continues to conduct and transistor 46 remains non-conducting. After the input voltage has passed its positive peak value and is decreasing negatively, all switching transients have terminated and the base electrode of transistor 46 is again at 0 v. The emitter electrode of transistor 46 is only a fraction of a volt less than the positive voltage applied to the base electrode of transistor 45 and, therefore, is positive with respect to the base electrode of transistor 46 at this time. When the signal applied to transistor 45 decreases negatively and reaches 0 v., transistor 46 becomes forward biased and commences to conduct. As the emitter current of transistor 46 starts to increase, the increasing voltage drop across resistor 50 decreases the forward bias of transistor 45. As the emitter current of transistor 45 decreases, the collector current thereof decreases, allowing the collector voltage to swing sharply positive. The positive swing at the collector electrode of transistor 45 is coupled by capacitor 47 to the base electrode of transistor 46, causing a sharp regenerative action which cuts off transistor 45 very rapidly and turns on transistor 46 very rapidly. As the input voltage now continues in its negative half cycle, transistor 46 continues conducting and transistor 45 continues non-conducting.

When transistor 46 is conducting the emitter current thereof is relatively constant, so that square waves of current appear at the collector electrode thereof. Because of the regenerative action, the slope of the leading edge of the current waveform will depend but little on the amplitude of the input signal applied to the base electrode of transistor 45, but will depend primarily on the circuit parameters of the regenerative comparator.

The signal available at the collector electrode of transistor 46 is employed as the output signal of the regenerative comparator.

The output signal of the regenerative comparator is coupled to an output amplifier, which functions to isolate the regenerative comparator from the clock pulse generator load, while preserving the steep wavefront of the waveforms generated. A transistor of the output amplifier and its associated circuit is adapted to receive the output signal of the regenerative comparator and to provide amplification thereof. When the collector electrode current of transistor 46 is zero, transistor 55 is maintained cut oil by the current passing through resistor 56, silicon diode 57 and resistor 58. At this time the clock pulse generator output signal from terminal 59 is 5 v. When transistor 46 is conducting the potential at the collector electrode thereof is sufficiently negative to provide forward bias for transistor 55, which thereupon conducts. When transistor 55 conducts the potential at output terminal 59 is approximately +5 v. The combination of silicon diode 57 and germanium diode 60 prevents transistor 55 from saturating, thus insuring more rapid cutofi of transistor 55 when transistor 46 is cut off.

An approximate waveshape of the output signal from terminal 59 is illustrated in the waveform immediately below output terminal 59.

Clock Pulse Driver The clock pulse driver of FIG. 3 provides clock pulse signals to drive other clock pulse drivers or for direct application to flip-flops and register transfers to control respectively the entry of data into flip-flops and the transfer of data between flip-flops. The clock pulse driver responds to positive trigger signals supplied by a clock pulse generator to generate corresponding clock pulses. The clock pulse driver may be gated to provide single clock pulses or clock pulses at the 250 kc. rate. When gated on, the clock pulse driver generates a clock pulse for each trigger signal received, but when gated off, no clock pulses are generated.

The clock pulse driver is basically a triggered blocking oscillator with output amplifier. A transistor 65, a transformer 66, a resistor 67, and associated biasing and power supply circuits, shown in FIG. 3, comprise the blocking oscillator portion of the clock pulse driver. A trigger signal supplied by the clock pulse generator is received at input terminal 68 and triggers the blocking oscillator to produce an output clock pulse. The trigger signal is only effective to trigger the blocking oscillator if the oscillator is not gated off by a negative voltage applied to gate terminal 69.

In the quiescent state, the base electrode of transistor 65 is at approximately +6.7 v., and transistor 65 is nonconducting due to the reverse bias applied thereto by the conduction of diode 70. The input trigger signals of the clock pulse generator have a peak-to-peak swing from -5 v. to +5 v., or a total excursion of about +10 v. When the gate input terminal 69 is enabled, a +6 v. signal is applied thereto. At this time the input trigger signal has suflicient amplitude to overcome the reverse bias applied to transistor 65.

The input trigger signal initiates the flow of a small emitter current in transistor 65. This, in turn, causes the flow of a small collector current through the primary winding of transformer 66. This increase in collector current in the primary winding of transformer 66 induces a voltage in the secondary winding thereof in a direction to apply a positive voltage to the emitter electrode of transistor 65. This induced voltage causes the emitter electrode to conduct more heavily. Thus, the circuit is highly regenerative and will quickly drive the transistor into saturation, wherein the impedance of the transistor between electrodes is substantially zero, and the entire applied voltage is developed across the transformer primary winding. The resulting large voltage developed across the secondary winding of transformer 66 saturates transistor 72 of the output amplifier, so that only resistor 67 limits the flow of emitter current in transistor 65. Since the total applied voltage appears across the primary winding of transformer 66, the collector current of transistor 65 rises linearly toward the maximum allowable value of collector current, as determined by the emitter current. The time for this current to rise to the maximum value is determined by the inductance of transformer 66.

When the collector current of transistor 65 reaches its maximum value, the resulting voltage induced in the transformer terminates. Another regenerative action takes place and the transistor cuts off rapidly.

When transistor 65 is conducting, transistor 72 conducts, and the clock pulse driver output signal, at terminal 73, is at approximately +6 v. When transistor 65 is nonconducting, transistor 72 is non-conducting, and the output signal from the clock pulse driver is clamped at -5 v. The clock pulse provided at terminal 73 is illustrated immediately below terminal 73.

When the clock pulse driver is gated oif, by application of a v. signal to terminal 69, a voltage drop of approximately 1 volt occurs across diodes 74 and 75. Thus, --4 v. is provided at the corresponding terminal of ca pacitor 76. The receipt of the input trigger signal, with swing of v., will drive the emitter electrode of transistor 65 to only +6 v. Inasmuch as the base electrode of transistor 65 is at +6.7 v., the transistor will not conduct and a clock pulse will not be delivered. Therefore, only when the clock pulse driver is enabled by the application of an appropriate gating signal thereto, will output clock signals be provided thereby.

If the clock pulse driver is to operate continuously and to provide an output clock pulse at a continuous 250 kc. rate, a +6 v. D.-C. bias is applied to input terminal 77.

Two symbols, shown in FIG. 3, are employed to represent the clock pulse driver. Symbol 80 represents a continuous clock pulse driver. Input trigger signals are received from a clock pulse generator by the input lead on the left-hand side of the block. Output clock pulses are delivered continuously from the output lead on the righthand side of the block. The symbol 81 represents a gated clock pulse driver. Input trigger signals are received at the left-hand terminal and gated output clock pulses are delivered at the right-hand terminal. The gating signal is applied to the terminal G" at the bottom of the symbol. The G terminal represents the gate input terminal 69 of the clock pulse driver. So long as the gating signal is at the 5 v. level, no output clock pulses are delivered from the right-hand lead. When the gating signal is increased to +6 v., the clock pulse driver delivers a clock pulse for every input trigger signal received. The gating signal is identified by the "Gate-" prefix. Thus, the gating signal applied to the SA clock pulse driver is identified as the Gate-SA signal.

Generally clock pulse drivers and their respective out- :put signals are identified in accordance with the function they perform. Thus, clock pulse drivers whose designations begin with the letter C," such as clock pulse driver CDAlZ, drive flip-flops and other clock pulse drivers. Clock pulse drivers driving register transfers generally have designations beginning with the letters 8" or X. The letter 5" denotes a clock pulse driver directing a serial shift of data. Thus, the clock pulse driver SA delivers the clock signal SA and provides a serial shift of the contents of the A-register. The letter X denotes a clock pulse driver directing a parallel shift, or transfer, of data. Thus, the clock pulse driver XAN provides a parallel transfer of data between the A-register and the N-register.

Flip-Flop The flip-flop of FIG. 4 provides temporary storage of a data word bit or provides temporary storage of a control signal. Generally, when a fiip-fiop is employed to store a data bit it comprises one of an array of flip-flops denoted as a register. For example, in a register adapted to provide temporary storage for a complete data word, 28 tzip-flops are employed, one for each bit of the data wor The flip-flop is a circuit adapted to operate in either one of two stable states, and to transfer from the state in which it is operating to the other stable state upon application of a trigger signal thereto. In one state of operation the flip-flop represents the binary 1 (l-state) and in the other state the binary 0 (O-state). The flipfiop circuit includes a pair of collector coupled transistor amplifiers, comprising the respective transistors 101, 102. The coupled transistor amplifier pair is connected to a pair of grounded-emitter transistor output amplifiers, the output signals thereof representing respectively the binary numbers 1 and 0, according to the stable state in which the flip-flop is operating. The two output amplifiers are designated respectively the l-output amplifier and the O-output amplifier, and comprise the respective transistors 103 and .104.

The flip-flop is adapted to receive five input signals; as follows:

(a) A clock pulse signal, received at input terminals and 105, and supplied by a clock pulse driver,

(b) An input logic signal for triggering the flip-flop to its l-state, received at input terminal 106, and usually supplied by a logical gate,

(1:) An input logic signal for triggering the flip-flop to its O-state, received at input terminal 107, and usually supplied by a logical gate,

(d) An input signal for triggering the flip-flop to its l-state, received at input terminal 108, and usually supplied by a register transfer circuit, and

(e) An input signal for triggering the flip-flop to its O-state, received at input terminal 109, and usually supplied by a register transfer circuit.

A flip-flop output signal representing the l-state of the flip-flop is delivered at output terminal and an output signal representing the O-state of the flip-flop is delivered at output terminal 111.

The operation of the fiip-fiop will now be described. In both of the stable states of the flip-flop one of transistors 101 and 102 is conducting and the other is nonconducting. Assume that transistor 101 is conducting and transistor 102 is not conducting. When transistor 101 conducts its collector electrode voltage is approximately at +8 v. This voltage, when coupled to the base electrode of transistor 102 causes the potential thereof to be approximately +8.3 v. and maintains transistor 102 in its non-conducting state. The flip-flop will continue in this state until application of a positive voltage greater than +8 v. to the base electrode of transistor 101. Transistor 101 will momentarily cease conducting. When transistor 101 ceases conducting, the collector electrode potential thereof becomes momentarily more negative. This negative change is coupled through capacitor 114 to the base electrode of transistor 102, which will then commence conducting. The collector electrode potential of transistor 102 will begin rising, and this potential rise will be coupled by a capacitor to the base electrode of transistor 101. The positive-going voltage coupled to the base electrode of transistor 101 tends to further decrease its tendency to conduct. This regenerative action continues until transistor 102 is in")! conducting and transistor 101 is non-conducting. At this time the flip-flop has transferred from the state in which it was operating to the other stable state.

When transistor 101 is conducting and transistor 102 is non-conducting the fiip-fiop is in its defined O-state, and when transistor 102 is conducting and transistor 101 is non-conducting the flip-flop is in its l-state. Thus, the state of operation of the flip-flop represents a binary digit.

When the flip-flop is in its 0state, the +8 v. of the collector electrode of transistor 101 is coupled to transistor 103 and maintains transistor 103 in a state of nonconduction. The signal provided at output terminal 110 at this time is at the --5 v. level. Inasmuch as the system logical elements and flip-flops respond to positive signals of approximately +6 v., the -5 v. delivered at output terminal 110 denotes a binary 0. Similarly, when transistor 101 is conducting, a negative voltage is coupled to transistor 104, so that transistor 104 conducts and dcli'vers a +6 v. signal at output terminal 111. The elements of the system are adapted to respond to the +6 v. signal, and it is, therefore, denoted as a binary 1. Therefore, when the flip-flop is in the O-state, a O-output signal is provided by the l-output terminal and a l-output signal is provided by the O-output terminal. Thus, system elements adapted to respond to the flip-flop 0- state will be enabled by the +6 v. signal delivered at terminal 111, whereas elements adapted to respond to the flip-flop l-state will be disabled by the 5 v. signal delivered at terminal 110.

Conversely, when transistor 102 is conducting, so that the flip-flop is in its l-state, a +6 v. signal, representing a binary 1, is supplied at terminal 110 and a -S v. signal, representing a binary 0, is supplied at terminal 111. Thus, the designation of output terminal 110 as a l-output terminal indicates that when the flip-flop is in its 1- state, a binary l-output signal is provided therefrom. The designation of terminal 111 as a O-output terminal indicates that when the flip-flop is in its O-state, a binary l-output signal is provided therefrom.

Consider now the input signals which will trigger the flip-flop; that is, those signals which will transfer the flip-flop from the state in which it is operating to its other stable state. The signals applied to terminals 106 and 107 result from the logical combination of other data-representing signals. When a logical combination represents a binary 0, the resulting logic signal is approximately 5 v. When a logical combination represents a binary l, the resulting logic signal is approximately +6 v. Inasmuch as +8 v. is applied to the emitter electrode of the one of the transistors 101 and 102 that is non-conducting, neither a O-logic signal nor a l-logic signal is adequate, alone, to trigger the flip-flop when applied to terminal 106 or 107.

The input logic signals applied to terminals 106 and 107 are coupled to the respective capacitors 116 and 117 and charge the corresponding capacitors to the logic voltage level. When a clock pulse is applied to terminals 105 and 105', the terminals will experience a positive voltage swing of approximately +11 v., as described in the previous section on the clock pulse driver. If a l-logic signal is present at terminal 106 or terminal 107, the clock pulse signal is superposed thereon and momentarily drives the corresponding base electrode of transistors 101 and 102 to +17 v., a voltage sutficient to momentarily cause the transistor to stop conduction, if it is conducting, and, therefore. to change the state of the flip-flop. However, any one of terminals 106 and 107 which is receiving a O-logic signal when the clock pulse occurs will cause a signal of but +6 v. to be applied to the base electrode of the corresponding flip-flop transistors, a signal insufiicient to change the state of the flip-flop. This type of flip-flop triggering is known as clock pulse pedestal triggering and enables the flip-flops of the system to change their state in synchronism with the clock pulses. Between clock pulses, which occur no more frequently than every 4 microseconds, there is adequate time for the logic elements of the system to change their state and for the resulting logical combination signals to stabilize at the logic input terminals 106 and 107 of all flip-flops. Then when clock pulses are applied to any one of the flipflops, the input logic signal levels will determine whether the flip-flop changes state. Since clock pulses are applied to both sides of the flip-flop simultaneously, only one of the logic inputs to the flip-flop is ordinarily permitted to be in the l-state at any given time. If both logic inputs are in the l-state, the clock pulse would attempt to turn off both transistors simultaneously and the flip-flop would not change its state. If both logic inputs are in the (It-state, the flip-flop does not change.

The diodes 119 and 120 isolate the input logic signal source from the flip-flop when the clock pulse occurs. The combination of the silicon and germanium diodes coupled to transistors 101 and 102 prevent saturation and are similar to those described for the clock pulse generator.

In addition to the input logic signal, which when enabled by a clock pulse. will trigger the flipflop, a register transfer input signal of proper amplitude, applied to terminals 108 or 109 will trigger the fiip-flop. The register transfer signal, usually provided by a register transfer circuit, consists of a logic signal with superposed clock pulse. Therefore, if the logic signal represents a binary 1, thereby having a +6 v. amplitude, the register transfer signal will be sufiicient to trigger the flip-flop. The superposed logic and clock signal is provided in the register transfer circuit to be described later. Therefore, the signals applied to terminals 108 or 109 are independently triggering, since they are adapted to trigger the flip-flop without requiring the clock pulses applied to terminals and 105. Register transfer circuits are generally employed to transfer the state of one flip-flop to another flip-flop and are, therefore, employed in transferring data between or within registers.

The register transfer input terminals are also employed for manually setting or resetting the flip-flop. A +12 v. signal is applied to the appropriate register transfer input terminal through a push-button or a switch. The +12 v. is adequate to transfer the flip-flop to the desired state.

Flip-flops are identified in accordance with the function they perform. For example, a typical flip-flop employed for control is identified as the Cwu flip-flop. The Cwu designation stands for Count W up," and the Cwu flipflop, when in the l-state, increases the count of the W- counter by 1. A typical flip-flop employed for temporary storage of data is the A41 flip-flop. When the A41 flip-flop stores a binary l, a +6 v. output signal is available at the l-output terminal thereof. The flip-flop of FIG. 4 is identified as the A41 flip-flop, and its input and output terminals are identified with the corresponding input and output signals of the A41 flip-flop.

The symbol 122, shown in FIG. 4, is employed to represent a flip-flop. Symbol 122, in this instance, represents the A4l flip-flop.

The A41 flip-flop is employed to temporarily store the l-bit of the 4th digit of the contents of the A-register. The five leads entering the left-hand side of the flip-flop symbol represent the five input terminals. The two upper input leads receive the l-input signals and the two lower leads receive the O-input signals. The central input lead receives the clock pulse signal.

The symbol indicates that the A41 flip-flop receives the clock signals of the B27 clock pulse driver. The first and fifth input leads to symbol 122 represent the respective register transfer input terminals 108 and 109. The notation #A4l opposite the first input lead, identifies the register transfer signal adapted to trigger the A41 flip-flop to the l-state. correspondingly, the notation #m opposite the fifth lead identifies the register transfer signal adapted to trigger the A41 flip-flop to the O-state. Similarly, the notations "A41 and "K 11 identify the logic input signals adapted to trigger the A41 fiip-fiop to the respective l and O-states. However, although the A41 or the K41 signal may represent a binary 1, it will not change the state of the flip-flop until the clock pulse driver B27 supplies a clock pulse. If only register transfer signals are applied to a flip-flop, no clock pulse driver is connected thereto, whereupon the notation n-c is placed opposite the clock pulse input terminal.

The two leads leaving the right-hand side of symbol 122 represent the two output terminals. The upper output lead delivers the l-output signal of the flip-flop and the lower output lead delivers the O-output signal. The notations A41 and A 11 identify the respective l-output and O-output signals of the A41 flip-flop. Thus, the notation A41 has the dual function of identifying the A41 flip-flop and of identifying the l-output signal thereof.

In the ensuing system description, a flip-flop in its l-state is also said to be in the set state or in the on" state. Conversely, a flip-flop in its O-state is also said to be in the "reset state or in the 011" state. When a flip-flop is transferred to its l-state it will often be said to be set or to be turned on." Conversely, when a flip-flop is transferred to its 0-state it may be said to be reset" or to be turned off."

AND-Gate The AND-gate of FIG. 5 provides the logical operation of Conjunction for positive input signals applied thereto. in the system a binary 1 is represented by a signal of approximately +6 v. Therefore, the AND- gate provides an output signal of approximately +6 v.,

representing a binary I, only when all of the input signals applied thereto represent binary 1's.

The AND-gate of FIG. 5 is illustrated, by way of example, as having three input terminals 126, 127 and 128, and a single output terminal 129. The AND-gates employed in the system are not limited to three input terminals, but may have from two input terminals to the maximum number necessary for the required Conjunctive operation.

A logic input signal applied to an input terminal of the AND-gate represents either a binary or a binary 1, and is provided as a corresponding signal of v. or +6 v. Current flows from a positive voltage source through resistor 139 and the diodes 131, 132 and 133 to respective terminals 126, 127 and 128. If any one of the input signals is at the -5 v. level, the corresponding diode will conduct and all other diodes of the AND-gate receiving +6 v. input signals will be back-biased and will not conduct. In such instance, the output signal from terminal 129 will be at -5 v. and represent a binary 0. Therefore, only when all input signals are at the +6 v. level will the output signal be at the +6 v. level.

The symbol 135, shown in FIG. 5 is employed to represent the AND-gate. Symbol 135 represents an AND- gate having three input terminals. The three input signals to the particular AND-gate shown are respectively denoted Tp, Tq and Ts. Therefore, the output signal 1s denoted Tp Tq Ts.

The expression Tp Tq Ts is the logic expression for the Coniunctive, or AND, combination of the individual signals Tp, Tq and Ts. This form of expression is used in logical equations, which are also known as Boolean equations, to be employed hereinafter. The Coniunctive operation on any two signals, such as the Tp and Tq signals, is indicated by writing the two signal terms adjacent each other with no operator notation therebetween, or with the operator notation between the two terms; as follows: Tp-Tq. This expression is read as Tp AND Tq. Oman The OR-gate of FIG. 6 provides the logical operation of Inclusive-Or for positive input signals applied thereto. The OR-gate provides an output signal of approximately +6 v., representing a binary 1, when any one or more of the input signals applied thereto represent binary ls.

The OR-gate of FIG. 6 is illustrated, by way of example, as having three input terminals 140, 141 and 142 and a single output terminal 143. The OR-gates employed in the system are not limited to three input terminals, but may have from two input terminals to the maximum number necessary for the required Inclusive- Or operation.

A logic input signal applied to an input terminal of the OR-gate represents either a binary 0 or a binary l, and is provided as a corresponding signal of -5 v. or +6 v. Current flows from the input terminals through the diodes 145, 146 and 147, and resistor 148 to a negative voltage source. If any one of the input signals is at the +6 v. level, the corresponding diode will conduct and all other diodes of the (JR-gate receiving 5 v. input signals will be back-biased and will not conduct. In such instance, the output signal from terminal 143 will be at +6 v. and will represent a binary 1. Therefore, when any one or more of the input signals are at the +6 v. level the output signal will be at the +6 v. level.

The symbol 149, shown in FIG. 6, is employed to represent the OR-gate. Symbol 149 represents an OR- gate having three input terminals. The three input signals to the particular OR-gate shown are respectively denoted Tp, Tq and Ts. Therefore, the output signal is denoted Tp+Tq+Ts.

The expression Tp+Tq+Ts is the logic expression for the Inclusive-0r, or OR, combination of the individual signals Tp, Tq, and Ts. This form of expression is used in the logical equations to be employed hereinafter. The Inclusive-Or operation on any two signals, such as the T and Tq signals, is indicated by writing the two signal terms adjacent each other with the operator notation therebetween; as follows: Tp-l-Tq. This expression is read as Tp OR Tq."

Inverter The inverter circuit of FIG. 7 provides the logical operation of Inversion, or NOT, for an input signal applied thereto. The inverter is adapted to provide an output signal of approximately +6 v., representing a binary 1, when the input signal received thereby has a 5 v. level, representing a binary 0. Conversely, the inverter provides an output signal representing a binary 0 when the input signal represents a binary l. The inverter supplies an additional output signal having the same logical significance as the input signal.

The inverter circuit of FIG. 7 comprises an emitter follower driving a grounded-emitter amplifier. The emitter follower portion of the inverter comprises a transistor having its output signal level clamped to have a total excursion between the extremes of +3.5 v. and +3.5 v. The input signal is applied at terminal 156. The output signal of the emitter follower is taken from the emitter electrode of transistor 155. This signal is also available at terminal 157 as a true logical representation of the inverter input signal. The output signal of the emitter follower is coupled to the grounded-emitter amplifier comprising transistor 158.

To analyze the operation of the inverter assume, first, that a binary 0 input signal is applied to input terminal 156. With an input signal of -5 v. level applied to the base electrode of transistor 155, the emitter electrode of transistor 155 operates approximately at the S v. level. However, junction point 160 is clamped to a 3.5 v. At this time current flows from the positive potential source through resistor 161, diode 162, and resistor 163 to the 3.5 v. junction point 160. The value of voltage at the base electrode of transistor 158 is below the value of +6 v., so that transistor 158 conducts and supplies a +6 v. output signal at output terminal 165. Thus, the inverter delivers an output signal representing a binary 1 when the input signal thereto represents a binary 0.

Assume, now, that the input signal represents a binary l. The application of a +6 v. signal to the base electrode of transistor 155 causes transistor 155 to cease conducting and establishes junction point 160 at the +3.5 v. level. The value of voltage at the base electrode of transistor 158 tends to go above +6 v., so that current flows through diode 166 and cuts off transistor 158. At this time the output signal at terminal is at the --5 v. level. Thus, a binary 1 input signal to the inverter provides a binary 0 output signal from terminal 165.

Capacitor 167 functions to speed the response of the inverter when the inverter input signal level changes from 5 v. to +6 v. Capacitor 168 prevents bypassing the diode 162, and thereby prevents saturation of transistor 153.

The symbol 170, shown in FIG. 6, is employed to represent the inverter. By way of example, the input signal to the inverter is denoted as the Sig signal. The logically inverted output signal provided at terminal 165 of the inverter is designated as T5175. The output signal provided from terminal 157 is not logically inverted and is represented by the legend ISig. Thus, the true" output signal of an inverter is usually identified with the letter I afiixed to the input signal term. The inverted output signal is similarly written, but is provided with a superscribing bar.

Emitter F ollower The emitter follower of FIG. 8 is employed in many parts of the logic networks of the system. The primary function of the emitter follower is to supply the input current requirements of a large chain of logical gates, which a tlip'fiop would be unable to directly drive. The specific locations of the emitter followers in the system will not be given in the description to follow. However, they may be employed following flip-flop output terminals or at other locations where large current requirements exist.

The emitter follower provides an output signal having the same logical sense as the input signal. That is, the emitter follower delivers a binary 1 output signal when the input signal represents a binary l, and vice versa. Two types of emitter followers are shown in FIG. 8. The first type, comprising the PNP transistor 175, is identified as a PNP emitter follower. The second type, comprising the NPN transistor 176, is identified as an NPN emitter follower. Generally, the PNP emitter follower drives an AND-gate and the NPN emitter follower drives an OR- gate.

The symbol 178, shown in FIG. 8, is employed to represent the emitter follower. The output signal of the emitter follower bears the same identification as the in put signal applied thereto.

Register Transfer The register transfer shown in FIG. 9 provides for the direct transfer of data between a pair of flip-flops. under control of a gated clock pulse driver. Normally, if a first flip-flop (which may be termed a data-receiving flip-flop) is adapted to receive the data bit stored in a second flip-flop (which may be termed a data-transmitting fiip-fiop), the register transfer input terminals of the first flip-flop are connected through respective register transfers to the corresponding output terminals of the second flip-flop.

The register transfer circuit of FIG. 9 comprises eight register transfers and is adapted to transfer the contents of four data-transmitting flip-flops, storing a full data digit, to four data-receiving flip-flops, also adapted to store a full data digit. A register transfer circuit is connected between the l-output terminal of each data-transmitting flip-flop and the register transfer l-inp-ut terminal of the corresponding data-receiving flip-flop. A register transfer is also connected between the -output terminal of each data-transmitting flipflop and the register transfer O-input terminal of the corresponding data-receiving flip-flop. FIGURE 10 illustrates the connection of a register transfer between an output terminal of a datatransmitting flip-flop and the corresponding register transfer input terminal of a data-receiving flip-flop.

The operation of a typical register transfer 201 of FIG. 9 will now be described. Register transfer 201, which is also shown in FIG. 10, is connected between the l-output terminal of the N21 flip-flop and the register transfer l-input terminal of the N11 flip-flop. The N21 flip-flop l-output terminal is connected to input terminal 202 of the register transfer circuit. Terminal 202 is connected to one end of resistors 203 and 204. The other end of resistor 203 is connected to a source of minus voltage. Resistor 203 provides collector resistance for the datatransmitting flip-flop output amplifier. Thus, the potential applied to input terminal 202 will be +6 v., when a binary l is applied thereto, and v. when a binary 0 is applied thereto. This input signal is transferred through resistor 204 and a diode 205 to output terminal 208. A capacitor 206 is connected to the junction of resistor 204 and diode 205, and is adapted to be charged to the logic voltage level provided by the corresponding data-transmitting flip-flop. Generally, the output signal of a gated clock pulse driver is connected to input terminal 207. Output terminal 208 is connected to the corresponding register transfer input terminal of the data-receiving flip-flop. A resistor 209 functions to discharge any stray capacitance connected across the output terminal 208, thereby preventing spurious triggering of the data-receiving flip-flop.

As described in the previous section entitled Flip- Flop," neither a 5 v. signal nor a +6 v. signal applied to the register transfer input terminal is sufiicient to trigger the flip-flop. However, when a clock pulse is superposed on a +6 v. signal, the flip-flop can be triggered. Thus, if a clock pulse is delivered by gated clock driver SN when a binary l-input signal is applied to input terminal 202, the superposed +6 v. and clock pulse delivered at terminal 208 will be adequate to trigger the data-receiving flip-flop.

The eight register transfers of FIG. 9 are adapted to transfer the entire contents of the second digit position of the N-registcr to the first digit position of the N-register upon receipt of the SN signal provided by the SN clock pulse driver. Inasmuch as a triggering output signal from a register transfer output terminal requires the simultaneous presence of a binary 1 from the corresponding data-transmitting flip-flop output terminal and a clock pulse at terminal 207, the register transfer output signal may be considered as representing a Conjunctive operation on the fiip-llop input signal and the clock pulse. Therefore, the output signal delivered at terminal 208, for example, may be represented as:

correspondingly, the output signal delivered at terminal 210 may be represented as:

The output terminals of one or more register transfers may be connected to a single register transfer input terminal of a flip-flop. In such instance, the one of the register transfers which has a clock pulse applied thereto will transfer the contents of the corresponding datatransrnitting flip-flop to the data-receiving flip-flop. An example of such a circuit is provided by the N11 flip-flop, which is adapted to receive the contents of the N21 flipflop when the SN clock signal is applied to register transfers connecting the output terminals of the N21 flip-flop to the corresponding register transfer input terminals of the N11 flip-flop, or to receive the contents of the All flip-flop when the XAN clock signal is applied to register transfers connecting the output terminals of the A11 fiipflop to the corresponding register transfer input terminals of the N11 flip-flop. This plural input connection to the register transfer l-input terminal of the N11 flip-flop is illustrated in FIG. 10.

Inasmuch as the plural register transfer connection to a flip-flop provides that an output signal from any one of the connected register transfers will trigger the datareceiving flip-flop, an Inclusive-Or logical operation is thereby provided for the output signals of the plurallyconnected register transfers. Thus, the register transfer l-input signal to the N11 flip-flop may be expressed as:

The output signals delivered by certain manually operated push buttons or switches are often directly connected to a flip-flop register input terminal which also has connected thereto one or more register transfers. Actuation of such a button or switch usually provides a +12 v. output signal, which is suflicient to trigger the data-receiving llip-fiop. Therefore, this type of connection also provides an Inclusive-Or logical operation for the output signals of the plurally-connected register transfers and the buttons or switches. For example, the register transfer O-input signal to the N11 flip-flop may be expressed as:

where Kcc is a +12 v. signal when certain buttons on the Control Console are depressed.

The symbol 212, shown in FIG. 9, is employed to represent the eight register transfers connecting the four flipfiops N24, N23, N22 and N21 to the corresponding ones of fiip-flops N14, N13, N12 and N11. The arrow in symbol 212 denotes that upon receipt of a clock pulse, the entire contents of N2(i) are transferred to N1(i). Terminal 207', which is shown connected to symbol 212, illustrates that this data transfer is effected only when a clock pulse SN is received. Symbol 213 represents the four flip-flops, N2(i), which are adapted to store the second digit of the contents of the N-registcr. Symbol 214 represents the four flip-flops, Nl(i), which are adapted to store the LSD of the N-register.

One-Shot The monostable multivibrator, or one-shot, of FIG. 11 provides an output signal of predetermined duration. The duration of the output signal is usually equal to a non-integral number of clock periods.

The one-shot is a circuit adapted to operate normally in a stable state, but to transfer to an unstable state for a predetermined duration upon application of a trigger signal thereto. In one state of operation the one-shot represents the binary l (l-state) and in the other state the binary (O-state). The one-shot circuit includes a pair of coupled transistor amplifiers comprising the respective transistors 220 and 221. The coupled transistor amplifier pair is connected to a grounded-emitter tran sistor output amplifier, the output signal thereof representing the 0-state of the one-shot. This output amplifier comprises a transistor 222.

The one-shot is adapted to receive two input signals; as follows: (a) a clock pulse signal, received at input terminal 223, and supplied by a clock pulse driver, and (b) an input logic signal, received at input terminal 224, and usually supplied by a logical gate.

The output signal, representing the O-state of the oneshot, is delivered at output terminal 225.

The operation of the one-shot will now be described. in the stable state transistor 221 is conducting and transistor 220 is non-conducting. The current flowing through the resistor 228 provides suilicient reverse bias voltage to maintain transistor 220 non-conducting, whereas this bias voltage is divided by resistors 229 and 230 to permit preferential conduction of transistor 221. The base electrode of conducting transistor 221 is approximately at ground, so that the emitter electrodes of transistors 220 and 221 are held negative with respect to ground by only a small voltage. The collector electrode of transistor 221 is also close to 0 v., so that transistor 222 is forward biased and conducts. The conduction of transistor 222 when the one-shot is in the stable state provides an output signal at terminal 225 of +6 v., representing a binary 1.

In the stable state the collector electrode of transistor 220 is approximately at +70 v. Therefore, capacitor 232, which is connected between the collector of transistor 220 and the base of transistor 221, is charged to +70 v.

A transistor 233 serves to isolate transistor 220 from the input terminals of the one-sbot. Normally, transistor 233 is non-conducting. The logic input signal applied to terminal 224 is either at the 5 v. level (binary 0) or at the +6 v. level (binary 1). Either level of the logic input signal is insufiicient to trigger the oneshot to its unstable state. However, if a clock pulse is applied to terminal 223 when the logic input signal is at its +6 v. level the superposition of the two input signals is sutficient to drive transistor 233 into conduction. This momentary high positive signal, approximately +17 v., is applied to the base electrode of transistor 220, which thereupon commences conduction. When transistor 220 commences to conduct, the collector electrode thereof experiences a sudden potential drop. This potential drop is coupled through capacitor 232 to the base electrode of transistor 221. As the base electrode of transistor 221 swings negatively, the collector current thereof diminishes. The decrease in current flow of transistor 221 reduces the reverse bias applied to transistor 220, which conducts more heavily. Thus, a regenerative action ensues, and transistor 220 is transferred to the conducting state and transistor 221 is rendered non-conducting. Transistor 221 remains cutoff by the high reverse bias applied to its base electrode from capacitor 232.

When transistor 221 is nonconducting, transistor 222 is rendered non-conducting, and the voltage at the output terminal 225 drops to 5 v. Thus, when the one-shot is in its unstable state, its output signal represents a binary 0.

Capacitor 232 now commences to discharge through the path provided. The discharge time of capacitor 232 is determined by the RC-time constant of the circuit loop comprising, basically. capacitor 232, potentiometer 234 and resistor 235. The discharge time is also influenced by the parallel-connected capacitor 236 and any one or more of capacitors 237, 238 and 239, which may be connected to the capacitor return terminal 240. The discharge time may also be altered by providing an external capacitor between the "ext time" terminal 241 and terminal 240.

In the unstable state, the emitter electrode of transistor 221 is slightly bclow ground potential. The base electrode thereof is held below ground in accordance with the voltage across capacitor 232. Therefore, as capacitor 232 discharges, the base electrode of transistor 221 rises toward the potential of the emitter electrode. When the base electrode potential reaches the emitter electrode potential, transistor 221 commences conducting, and the one-shot returns to its stable state, where it remains until it is again triggered.

One-shots are identified in accordance with the function they perform, although all one-shot designations begin with the letter Y. For example, the Ybl designation refers to a one-shot which controls the time duration of the ringing of a bel. Normally only the O-output signal is taken from the one-shot. That is, when the one-shot is triggered into its unstable state, the logic sig nal available at the output terminal of the one-shot represents a binary O. In its stable state the one-shot output signal represents a binary 1. Thus, in effect, the oneshot output signal turns oil when the one-shot is triggered. If desired, another output amplifier may be connected to the collector electrode of transistor 220 to provide an output signal representing the l-state of the one-shot. Such an amplifier would provide a binary 1 when the one-shot was in its unstable state.

The symbol 244, shown in FIG. ll, is employed to represent the one-shot. Symbol 244, in this instance, represents the Ybl one-shot. The two leads entering the left-hand side of symbol 244 represent the two input terminals. The upper input lead receives the logic input signal. The lower input lead receives the clock pulse signal. The symbol indicates that the Ybl fiipflop receives the clock pulses provided by the CDAlZ clock pulse driver. The notation "Ybl opposite the upper input lead identifies the logic input signal. The lead leaving the right-hand side of symbol 244 represents the output terminal. The notation YET identifies the 0-out put signal of the Ybl one-shot. The duration of the unstable state of the flip-flop is also included within the symbol. Thus. the unstable state of the Ybl fiip-flop is indicated to be 15 ms.

Register A register is adapted to provide temporary storage of data being processed or data being transferred between system components. The register comprises a plurality of flip-flops, one flip-flop for each bit of the data to be stored therein. Most registers of the system store a full data word and, therefore, comprise 28 flip-flops.

The fiip-fiops of a register are identified according to the register designation and the numerical significance of the data bits stored therein. Thus, a register fiip-fiop will be designated as the Qmn fiip-fiop, where Q identifies the register, m identifies the digit order of the bit stored, and n identifies the decimal significance of the bit stored. For example, the J13 flip-flop stores the 4-bit of the least 27 significant digit of the J-register contents. The 28 flipflops of the J-register may be represented; as follows:

J-REGISTER J11 (J74) J64 J54 J44 J34 J24 J14 Js (J73) J63 J53 J43 J33 J23 J13 11112 (J72) J62 J62 J42 J32 J22 J12 Jml (J71) J61 J51 J41 J31 J21 Ill The most significant, or 7th, digit of the data word is stored in Id, Is, Jm2 and Jml. This set of flip-flops is also termed J74, J73, J72 and 171.

The data in most of the registers may be serially shifted from higher to lower order digit positions of the register. In such registers, the entire contents of a digit position are transferred by parallel shift to the next lower order digit position. The serial shifting of data in this manner is most often effected by register transfers connected between the flip-flops (see FIGS. 9 and in the section "Register Transfer). Data which is serially transferred by digits to successively lower order digit positions is said to be shifted-down. If the flip-flops are interconnected to transfer the data to successively higher order digit positions, they are said to "shift-up" the data.

If the digit in the LSD position is directed to re-enter the register at the MSD position during a shift-down, the data is said to be ring shifted-down." Conversely, if the MSD position digits enter the LSD position, the data is said to be ring shifted-up."

Temporary signal storage is provided to permit a register flip-flop to change its state at the same time that its contents are being transmitted to another register flipflop; i.e., during the serial shift of data in a register. This temporary signal storage is supplied by capacitors in the register transfers and in the flip-flop logic input circuits. These capacitors store the logic signal levels from the output terminals of a data-transmitting flip-flop prior to the occurrence of the clock signal that causes the data-transmitting flip-flop to change its state and the corresponding data-receiving flip-flop to receive the contents of the data-transmitting flip-flop. Thus, the register transfer capacitors 206 temporarily store the logic signal levels provided by the data-transmitting flip-flop. When the clock pulse is applied to the register transfer the contents of the data-transmitting flipfiop are held in capacitors 206 sufficiently long for the data-receiving flipfiop to respond thereto, while the data-transmitting flipflop may simultaneously have the state thereof changed. Similarly, where the contents of one flip-flop are transmitted to another through logical gates, the flip-fiop input capacitors 116 and 117 provide temporary storage for the input logic signal levels.

DATA PROCESSING SYSTEM-DETAILS The Data Processing System is shown symbolically in FIG. 12 to illustrate the elements therein which store data, the paths of data transfer between these elements, and major control elements of the system.

Instruction words for data processing, and operand words which are to be processed are stored in the 4,000 word Core Memory during data processing operations. Temporary storage of data words is provided in the various registers of the system. Data is most often transferred between registers by means of register transfers, not shown in FIG. 12. Most registers are also adapted to shift the data therein by the employment of register transfers between digit positions, such as shown in FIG. 9.

The instruction word which directs the system operation is stored in the I-register 272. The I-register comprises two registers, a 2-digit C-register and a 4-digit A- register. The I-register stores the 6 least significant digits of an instruction word, these digits including the command portion and the address portion. The command portion is stored in the C-register and the address portion in the A-register. The command portion in the C- register controls the type of operation to be executed by the system. The address portion in the A-register usually indicates the memory location from which the operand word is to be received, or where a data word is to be stored. However, the address portion is also employed as a control function to supplement the command portion in controlling the type of operation to be executed. The memory location of the next instruction to be executed is stored in the 4-digit N-register 274. As execution of an instruction is nearing completion the nextinstruction address stored in the N-register is transferred to the A-register, and this address provides the Memory Controls 242 with the information to obtain the next instruction from the Core Memory 243.

All data words received from the Core Memory or entered into the Core Memory must pass through the 7-digit M-register 245. Therefore, when an instruction is to be received from the Core Memory the A-register contents direct the Memory Controls to obtain the instruction from the location then indicated in the A-register. This instruction is first transferred to the M-register and then to the 7-digit J-register 271. From the I-register the 6 least significant digits of the instruction word are transferred to the I-register and the instruction is then executed. Operand words needed by the instruction are obtained from the Core Memory by the same process; that is, by a first transfer to the M-register under control of the address portion of the instruction word in the A- register and then by a transfer to the J-register.

Arithmetic operations, sorting operations, comparison operations, etc., on operand words are performed primarily by employing the Arithmetic Unit 276, the L- register 273, and the R-register 275, The L-register and R-register are both 7-digit registers and each stores a complete data word. The L and R-registers are employed together when data processing is performed on double-precision words, and when so employed are designated as the FULL-register. The R-register is usually employed when processing single data words. The Arithmetic Unit is adapted to perform the operation of addition or subtraction on a pair of words received simultaneously from the J-register and the R-register or on data received simultaneously from the A-register and the B-register 270. When the contents of I and R are received by the Arithmetic Unit the output signals thereof are entered into the R-register, if single numeric words are being processed, and into the FULL-register if doubleprecision words are being processed.

A data word in the R-register may be transferred to the M-register for storage in the Core Memory at the location designated by the A-register contents.

The 4-digit B-register is employed to modify the ad dress portion of the instruction word in the A-register. This modification is performed by adding the B-register contents to the A-register contents in the Arithmetic Unit, and by entering the output signals of the Arithmetic Unit into the A-register.

The Ar-register 268 and the Aw-register 269 store memory addresses during respective Multiplex Buffer read and write operations and are adapted to enter the address into the A-register when the Multiplex Buffer is to transfer a word to the Core Memory or to receive a word therefrom.

The modulo-3 of all words received by the I-register from the Core Memory is compared against the mod-bits of these words by the J'mod-generator 277, which accumulates the modulo-3 of a word as it ring shifts in the J-register. The V-mod-generator of the Arithmetic Unit accumulates the modulo-3 of the Arithmetic Unit output signals in order to apply the appropriate mod-bits to this word.

The Ar, Aw, B, I, I, L, N, and R-registers, the Arithmetic Unit, and the J-mod-generator comprise the Central Processor 10 of FIG. 1. The Memory Controls,

29 Core Memory, and M-register comprise the Memory 12 of FIG. 1.

The Central Processor receives data from the Control Typewriter, the Photoreader, the Tape Handlers, and the Character Reader, and transmits data to the Tape Handlers, the Printer, the Control Typewriter, and the Sorter.

The 7-digit P-register 247, which is a part of the P- Buffer, temporarily stores a data word being transferred from the Control Typewriter or from the Photoreader to Memory. The P-register also temporarily stores a data word being transferred from Memory to the Control Typewriter. In so exchanging data with the Memory, the P-Buifer is controlled by the Central Processor and its mode of operation is initiated by the contents of the A-register, which sets the P-Buffer Controls 246. The P-Buffer, when directed by the Control Typewriter, coordinates the typing out of the contents of the B, I, L, N, P, and R-registers by the Control Typewriter. The Control Typewriter and the P-Buffer also cooperate in entering data words directly into the I-register and the R-register.

The Rib-register 248 and the Wb-register 250 form a part of the Multiplex Buffer and are controlled by the Multiplex Buffer Controls 249. The 7-digit Rb-register temporarily stores a data word being transferred from magnetic tape or the Sorter Control Unit to Memory. The 7-digit Wb-register temporarily stores a data word being transferred from Memory to magnetic tape or to the Printer.

A description of the system operation is provided in a succeeding section entitled Instructions, and in the sections following thereafter. Details of the system structure and of the components thereof are provided in FIGS. 17, 19, 20, 24, 28, 29, 33, 36, 37, 42, 43 and 48-187.

Data Processing Operations The command portions of the instruction word may have any one of 52 bit configurations, each configuration representing a different one of 52 decimal numbers. Each command portion number directs a fundamentally different data processing operation of the system. The system executes the commands of a succession of instruction words to process data. This succession of instruction words is termed a program, in any program many, or all, of the 52 fundamental operations are executed one or more times to process the received data.

These fundamental operations which the system will execute, may be grouped by function; as follows:

A. Memory Input-Output Operations Instruction 75: Transfer M to R (TMR) A data word in Memory is transferred to the R-register. Instruction 70: Transfer R to M (TRM) The data word in the R-register is transferred to Memory. Instruction 21: Exchange R and M (XMR) The data Word in the R-register is transferred to a specified memory location and the data word in that location is transferred to the R- register. Instruction 85: Transfer M to FULL (TMF) A double-precision word in Memory is transferred to the L and R-registers (FULL). Instruction 80: Transfer FULL to M (TFM) The double-precision word in FULL is transferred to Memory.

B. Operations Shifting Data within the Central Processor Instruction 94: Exchange R and B (XRB) The entire contents of the B-rcgister are exchanged with the four least significant digit position contents of the R-register.

30 Instruction 97: Exchange L and R (XLR) The L and R-registers exchange data words. Instruction Shift R Right (N) (SI-IR) The numeric portion of the data word in the R-register is shifted-down through a designated number (N) of digit positions.

Instruction 91: Ring Shift R (N) (RSR) The numeric portion of the data word in the R- register is ring shifted-down through a designated number (N) of digit positions.

Instruction 92: Shift FULL Right (N) (SHF) The combined numeric portions of the doubleprecision data word in FULL is shifted-down through a designated number (N) of digit positions.

Instruction 93: Ring Shift FULL (N) (RSF) The combined numeric portions of the doubleprecision data word in FULL is ring shifteddown through a designated number (N) of digit positions.

Instruction 28: Transfer M to B (TMB) The four least significant digits of a data word in Memory are transferred to the B-register.

. Program Jump Operations Instruction 60: Branch if Dl (BDl) The sequence of instructions being executed will be interrupted by a jump to a designated instruction, if the D1 flip-flop is on.

Instruction 62: Branch if D2 (BD2) The sequence of instructions being executed will be interrupted by a jump to a designated instruction, if the D2 flip-flop is on.

Instruction 64: Branch if D3 (BD3) The sequence of instructions being executed will be interrupted by a jump to a designated instruction if the D3 flip-flop is on.

Instruction 63: Jump Unconditionally (JUN) The sequence of instructions being executed will be interrupted by a jump to a designated instruction.

Instruction 61: Jump Unconditionally, Transfer N to B (JNB) The sequence of instructions being executed will be interrupted by a jump to a designated instruction, and the contents of the N-register are transferred to the B-register.

. Comparison Operations Instruction 76: Is R Greater Than M? (RGM) The data word in the R-register is compared with a specified data word in Memory, and if the word in the R-register is greater than the word in Memory, the D1 flip-flop is set.

Instruction 86: Is L-R Greater Than M and M -l-l? (FGM) The double-precision word in FULL is compared with a specified double-precision word in Memory, and if the word in FULL is greater than the word in Memory, the D1 flip-flop is set.

Instruction 71: Is R Unequal to M? (RUM) The data word in the R-register is compared with a specified data word in Memory, and if the two words compared are not equal, the DI flip-flop is set.

Instruction 81: Is L-R Unequal to M and M +1? (FUM) The double-precision word in FULL is compared with a specified double precision word in Memory, and if the two words compared are not equal, the D1 flip-flop is set.

31 Instruction 31: Find Word in Memory Equal to LR (FND) The Memory is searched through a series of sequential double-word locations to find a double-precision word that is equal to the double-precision word in FULL.

Instruction 36: Find Word in Memory Equal To or Greater Than FULL (FGR) The Memory is searched through a series of sequential doubleword locations to find a double-precision word that IS equal to or greater than the double-precision word in FULL.

. Sorting Operation Instruction 35: Tumble (TUM) The double-precision word in FULL is stored in Memory at a designated double-word location. and the double-precision words in the designated memory location and in following sequential double-word memory locations are each shifted to the next sequential doubleword locations.

. Arithmetic Operations Instruction 72: Add M to R (AMR) A word in Memory is added to the word in the R-register, and the sum is placed in the R- register.

Instruction 73: Subtract M from R (SMR) A word in Memory is subtracted from the word in the R-register, and the difference is placed in the R-register.

Instruction 82: Add M to FULL (AMF) A double-precision word in Memory is added to the double-precision word in FULL. and the sum is placed in FULL.

Instruction 83: Subtract M from FULL (SMF) A double-precision word in Memory is subtracted from the double-precision word in FULL, and the difference is placed in FULL.

Instruction 87: Add M to R and Carry (ARC) A word in Memory is added to the word in the R-register, and the sum is placed in FULL. Instruction 88: Subtract M from R and Carry (SRC) A word in Memory is subtracted from the word in the R-register, and the difference is placed in FULL.

Instruction 27: Add M to B (AMB) The four least significant digits of a data word in Memory are added to the contents of the B-registcr, and the sum is placed in the B- register.

Instruction 42: Multiply M by R (MPY) A word in Memory is multiplied by the numeric portion of the word in the R-register, and the product is placed in FULL.

Instruction 43: Divide FULL by M (DIV) The numeric portion of the double-precision word in FULL is divided by the numeric portion of a single numeric word in Memory, and the quotient is placed in FULL.

. Miscellaneous Central Processor Operations Instruction 25: Mod-3 Generation on R (GMR) Mod-bits are generated for the modulo-3 of the numeric portion of the R-register contents. Instruction 26: Mod-3 Generation on L and R (GMF) Mod-bits are generated for the modulo-3 of the numeric portions of both the L and R-registers. Instruction 54: Does Condition X Exist? (DSW) One or more of a plurality of interrogations relating to conditions in various parts of the system are made, and if the condition or conditions exist, the D3 flip-flop is turned on.

32 Instruction Change State of Sign or Designator of R, or Change Jc (Cl-IR) The state of the 10, Rd, and Rs flip-flops may be altered.

Instruction 29: Extract M into R by L (EXT) Certain digits of the word in the R-register are replaced with the corresponding digits of a word in Memory, under control of a word in the L-register.

Instruction 53: Halt (I-ILT) Data processing halts at the termination of the instruction.

. System Input-Output Operations Instruction 24: Transfer P to M (TPM) The data word in the P-register is transferred to Memory.

Instruction 74: Transfer M to P (TMP) A data word in Memory is transferred to the P-register.

Instruction 59: Photoreader or Control Typewriter In or Out (PIO) A data word is transferred into the P-register from either the Photoreader or the Control Typewriter, or the data word in the P-register is transferred to the Control Typewriter.

Instruction 52: Ring Bell or Gong (RNG) An audible indication is produced.

Instruction Read Magnetic Tape or Character Reader (RMT) The Multiplex Buffer is directed to start reading one block of data from magnetic tape or to start reading one line of data from a document.

Instruction 66: Write Magnetic Tape or Load Printer (WMT) The Multiplex Buffer is directed to start writing one block of data onto magnetic tape or to start transmitting one block of data. to the Printer.

Instruction 67: Alter Magnetic Tape (AMT) The magnetic tape of a Tape Handler is caused to reverse, erase, or rewind.

Instruction 68: Write Blockettes on Magnetic Tape or Load Printer (WMB) The Multiplex Butter is directed to start writing 5 blockettes of data onto magnetic tape, or to start transmitting 5 blocltettes of data to the Printer.

Instruction 58: Start or Stop Check Feeding (CHF) The Sorter is directed to start or stop transferring documents to the Character Reader.

Instruction 57: Select Sorter Pocket (N) (POC) The Sorter is directed to store the next document in a designated (N) pocket.

In addition to the 49 above-described programmable operations. three different operations are directed by the corresponding command portion numbers 51, 5S, and 56. These three numbers are automatically inserted into the C-register when data is being transferred into or out of the Multiplex Buffer. One of these operations is employed each time the program or an instruction is interrupted in order to transfer data between the Memory and the Multiplex Bufier.

Under certain circumstances an Instruction 25 or 26 is entered automatically to provide the correct mod-bits after an instruction has altered the modulo-3 of a word.

GLOSSARY AND INDEX OF SIGNALS The signals provided by the system circuit elements are tabulated below. The portion of the description which illustrates or describes the respective source circuit element for each of these signals is also identified.

For example, the notation:

Anpd: FF, Cent Proc; FIG. 105

indicates that the Anpd signal is provided by the Anpd flip-flop of the Central Processor, and that the source flip-flop and the corresponding logical schematic diagrams for providing input signals thereto are illustrated in FIG. 105. A similar notation is employed for one-shot and inverter output signals.

The notation:

Cad: Log, Cent Proc; FIG. 107

indicates that the Cad signal is a designated logical combination signal of the Central Processor, and that its source logical schematic diagram is illustrated in FIG.

The notation:

B27: CP, Cent Proc; FIG. 17

indicates that the B27 signal is provided by the B27 clock pulse driver of the Central Processor. Since the B27 clock pulse driver operates continuously, FIG. 17" refers to the actual illustration of the B27 clock pulse driver. However, if a clock pulse driver is gated, the noted figure refers to the illustration showing the logical schematic diagram for providing the gating signal for the clock pulse driver which supplies the tabulated signal. Thus, the B28 gated clock pulse driver output signal is tabulated as B28: CP, Cent Proc; FIG. 108 wherein FIG. 108 illustrates the logical schematic diagram that provides the Gate-B28 signal for the B28 clock pulse driver.

The notation:

Kccc: Sw, Con Cons; FIG. 19 indicates that the Kccc signal is provided by closing a switch or button on the Control Console.

The notation:

Ka: Key, Con Typ; Control Typewriter" section indicates that theKa signal is provided by depressing a key on the Control Typewriter. The source circuit element for the Ku signal is not illustrated in the drawings, but is described in the Control Typewriter" section.

The notation (ii) following the identification of a flipflop indicates, generally, all flip-flops of a given register which bear a numerical suffix. For example, A(ii) refers to the signals delivered by all flip-flops of the A- register.

The table to follow employs the abbreviations: CP-Clock pulse driver F F-Flip-fiop I nv-Inverter KeyKey Log-Designated logical combination signal OSOne-shot SwSwitch or button Cent ProcCentral Processor Char Rdr--Character Reader Con ConsControl Console Con Typ--Control Typewriter Mem-Memory MultBut-Multiplex Butter P-BufP-Buffer PhotoPhotoreader PrLr-Printer Read-BufRead Bufier Sort-Sorter Sort Con-Sorter Control Unit Tape Con-Tape Control Unit Tape HanTape Handler Write-Buf-Write Butler A(ii): FF, Cent Proc; FIGS. 48-51 The l-output signals of the 16 flip-flops of the A- register, which stores the address portion of the instruction word.

34 Aac: FF, Cent Proc; FIG. 98

The l-output signal of an alarm flip-flop which is set to the l-state if a malfunction occurs in the Arithmetic Unit.

Ah: Sw, Con Cons; FIG. 19

A signal which issues upon depression of the AD- DRESS HALT button and causes the system to halt when a designated address is in the A-register. Ai: FF, Cent Proc; FIG.

The l-output signal of an alarm flip-flop which is set to the l-state if an improper instruction word enters the Central Processor.

AM(ii): FF, Mem; FIGS. -113 The l-output signals of the 14 fiip-lops of the AM- register, which stores the address of the memory location addressed during each memory cycle. Amm: FF, Cent Proc; FIG. 105

The l-output signal of an alarm flip-flop which is set to the lstate if an improper data wo d is transferred to the Central Processor from Memory. Anpd: FF, Cent Proc; FIG. 105

The l-output signal of a sub-alarm flip-flop which is set to the l-state if the Central Processor fails to select a Sorter pocket after a document is read by the Character Reader.

Ar(ijl: FF, Cent Pioc; FIGS. 52-5$ The l-output signals of the 14 flip-flops of the Arregistcr, which stores the memory location wherein the next word to be read from magnetic tape or the Character Reader is to be stored. Aid: FF, Tape Con; Alarms" section The l-output signal of an alarm flip-flop which is set to the l-state if the addressed Tape Handler is disabled.

Ate: FF, Cent Proc; FIG. 105

The l-output signal of an alarm flip-flop which is set to the l-state if a malfunction occurs when a Tape Handler or the Character Reader is reading or when a Tape Handler or the Printer is writing. Arm: FF, Cent Proc; FIG. 104

The l-output signal of a control flip-flop which, when set to the l-state, causes the word in the M- register of the Memory to be incremented by 2 as it is restored to its Core Memory location. Aw(ij): FF, Cent Proc; FIGS. 56-59 The l-output signals of the 14 flip-flops of the Awregister, which stores the memory location wherein the next word to be written by a Tape Handler or the Printer is stored.

B17: CP, Cent Proc; FIG. 17

The clock pulses which are delivered by a continuous clock pulse driver and which are applied to clock pulse input terminals of Central Processor flip-flops. B27: CP, Cent Proc; FIG. 17

The clock pulses which are delivered by a continuous clock pulse driver and which are applied to clock pulse input terminals of Central Processor flip-flops. B28: CP, Cent Proc; FIG. 108

The clock pulses which are delivered by a gated clock pulse driver and which are applied to clock pulse input terminals of Central Processor flip-flops. B(ij): FF, Cent Proc; FIGS. 60-63 The l-output signals of the 16 flipflops of the B- register, which stores a number for modifying the address in the A-register. Bb: FF, Cent Proc; FIG. 95

The l-output signal of a control fiip-fiop which, when set to the l-state, causes modification of the address in the A-register effecting the addition thereto of the contents of the B-register.

35 Bbf: FF, Write-But; FIG. 154

The l-output signal of a control flip-flop, which when set to the l-state, signals that the first word of a block of data words has been transferred to the Write Buffer or aids in terminating the transfer of a block of data words to the Printer. Bbs: Log, Write-But; FIG. 158

A signal which notifies the Printer that the first word of a block of data words is ready to be transferred thereto. Bkr: Log, Cent Proc; FIG. 107

A signal which directs a Tape Handler to back one data block. Blk: FF, Cent Proc; FIG. 104

The l-output signal of a control flip-flop which, when set to the l-state, directs the writing on magnetic tape or by the Printer of 100 data words comprising five blockettes of 20 Words, wherein the five blockettes are taken from five respective groups of memory locations disposed at random in Memory, each group comprising 20 consecutive memory locations. Bis: Log, Cent Proc; FIG. 107

A signal which counts the Whit-counter up by 1 whenever the write-memory address in the A- register is a multiple of 20. Brt: FF, P-Buf; FIG. I35

The l-output signal of a control flip-flop which, when set to the l-state, directs the type-out of the contents of a designated register by the Control Typewriter when the Central Processor is halted. C(ii): FF, Cent Proc; FIGS. 64, 65

The l-output signals of the 8 flip-flops of the C- register, which stores the command portion of the instruction word. Cad: Log, Cent Proc; FIG. 107

A signal which effects the decrease by 1 of the number represented by the contents of the A21 and the Al flip-flops of the A-register. Can: Log, P-Buf; FIG. 138

A signal which directs the transfer of the contents of the P7 flip-flops to the Cs flip-flops of the P- Bufler when data is being transferred from the P-Bufier to the Control Typewriter. Cap: CP, P-Buf; FIG. 138

The clock pulses which are delivered by a gated clock pulse driver and which are applied to clock pulse input terminals of P-Buffer flip-flops. Cau: Log, Cent Proc; FIG. 107

A signal which effects the increase by l of the numerical portion of the contents of the A-register. Ca'0-Cd9: Char Rdr; FIG. 42

Signals delivered by the Character Reader which represent the reading and recognition of the respective numerals -9 on a document. CD1, CD2: CP, Mult-Buf; FIG. 33

The clock pulses which are delivered by a pair of continuous clock pulse drivers and which are applied to clock pulse input terminals of Multiplex Buffer flip-flops and one-shots. CD3: CP, Tape Con; FIG. 33

The clock pulses which are delivered by a continuous clock pulse driver and which are applied to clock pulse input terminals of Tape Control Unit flipflops. CD4: CP, P-Buf; FIG. 29

The clock pulses which are delivered by a continuous clock pulse driver and which are applied to clock pulse input terminals of P-Bufier fiipflops and one-shots. CDA, CDB, CDC: CP, Cent Proc; FIG. 17

The clock pulses which are delivered by three continuous clock pulse drivers and which are applied to drive other clock pulse drivers of the Central Processor.

36 CDAll, CDA13, CDA14: CP, Cent Proc; FIG. 17

The clock pulses which are delivered by three gated clock pulse drivers and which are applied to clock pulse input terminals of Central Processor flipflops. CDA12: CP, Cent Proc; FIG. 17

The clock pulses which are delivered by a continuous clock pulse driver and which are applied to clock pulse input terminals of Central Processor flipflops and one-shots. Cer: Char Rdr; FIG. 42

A signal which is delivered by the Character Reader to denote that the Character Reader has been unable to read or to recognize a particular character on a document. Cfd: FF, Cent Proc; FIG. 104

The l-output signal of a control flip-flop which, when set to the l-state, causes the Sorter Control Unit to direct the Sorter to continuously feed documents. Cfs: FF, Read-But; FIG. 177

The l-output signal of a control flip-flop which, when set to the l-state, controls the Read Buffer so that .a line of data is read from but one document. Cfsa: Log, Cent Proc; FIG. 107

A signal which effects the resetting of the Rab flipflop after a character reading command has been given, but during the duration of which no document has been detected, by causing the setting of the Cfs flip-flop. Cha: FF, Read-But; FIG.

The l-output signal of a control flip-flop which, when set to the l-state, controls the Read Buffer when data is being transferred thereto from the Character Reader. Chad: Log, Ccnt Proc; FIG. 107

A signal which prepares the Read Buffer and Character Reader for a character reading operation by causing the setting of the Cha flip-llop in the Read Buffer. Cinf: Log, P-Buf; FIG. 138

A signal which directs the transfer of the character transmitted by the Control Typewriter to the Cs flip-flops of the P-Bufier. Cinp: Log, P-Buf; FIG. 138

A signal which directs the transfer of the character transmitted by the Photoreader to the Cs flipflops of the P-Bufi'er. Cinr: Log, P-Buf; FIG. 138

A signal which directs the transfer of the contents of the P7 flip-flops, or of the P7 and PI flipfiops, to the Cs flip-flops of the P-Bufler, when data is being transferred from the P-Bufier to the Control Typewriter. Ckp: FF, Sort Con; FIG.

The l-output signal of a control flip fiop which, when set to the l-state, signals that the field of a document is passing the transducer of the Character Reader. Cid: Log, Cent Proc; FIG. 107

A signal which effects the decrease by l of the contents of the Ll flip-flops of the L-register. Clu: Log, Cent Proc; FIG. 107

A signal which efiects the increase by l of the contents of the L1 flip-flops of the L-register. Cod4-Codl: Log, Sort Con; FIG. 187

The signals delivered by the digit encoder 850 of the Sorter Control Unit, which represent in four bit complementary code the numeral read and recognized by the Character Reader. Cof: FF, Sort Con; FIG. 185

The l-output signal of a control flip-flop which,

when set to the l-state, directs the Sorter to continuously feed documents.

Cpg: Log, Cent Proc; FIG. 107

A signal which issues during a greater than" comparison instruction to enable various logic inputs to D1, in order that D] may reflect the result of a "greater than" comparison. Crd4-Crdl: Log, Sort Con; FIG. 187

The signals transmitted from the Sorter Control Unit to the Read Buffer, which represent in four bit complementary code the character read and recognized by the Character Reader. Csl-Csfi, Csp: FF, P-Buf; FIGS. 130, 131

The l-output signals of the 7 fiip fiops oi the Csregistcr, which stores the six data bits and the parity bit of characters being transferred into the P-Buffcr from the Control Typewriter and the Photoreader or being transferred out of the P- Butfer to the Control Typewriter. Cscl, Csc2: CP, Sort Con; FIG. 43

The clock pulses which are delivered by a pair of continuous clock pulse drivers and which are applied to clock pulse input terminals of Sorter Control Unit flip-flops and one-shots. Csu: FF, Read-Buf; FIG. 177

The l-output signal of a control flip-flop, which controls the bursts of the Tr-counter when data is being read by the Character Reader and transferred to the Read Buffer, and also signals the failure of a Tape Handler to transfer any data to the Read Buifer during the reading of a block of data from magnetic tape. Csyl, Cs'yZ, Csy3: OS, Sort; FIG. 42

The output pulses of three cascaded Sorter one-shots which operate to synchronize the reading of a line of data from a document and the subsequent insertion of the document in a Sorter pocket when a pocket decision is received by the Sorter. Cu4-Cul: Char Rdr; FIG. 42

Signals delivered by the Character Reader which represent the reading and recognition of the respective cue characters on a document. Cwu: Log, Cent Proc; FIG. 107

A signal which effects the increase by l of the contents of the W-counter. Cytc: CP, P-Buf; FIG. 138

The clock pulses which are delivered by a gated clock pulse driver and which are applied to clock pulse input terminals of P-Butfer flip-flops. Dl: FF, Cent Proc; FIG. 100

The l-output signal of a control flip-flop which, when set to the l-state, indicates the results of the execution of certain comparison instructions. D2: FF, Cent Proc; FIG. 100

The l-output signal of a control flip-flop which, when set to the l-state, indicates that the two least significant digits of the contents of a memory address have been incremented by 2, and also indicates that an overflow has occurred when the four least significant digits of a word in Memory are added to the contents of B, during execution of an Instruction 27. D3: FF, Cent Proc; FIG. 100

The l-output signal of a control flip-flop which, when set to the l-state, indicates that a particular situation exists during execution of an interrogation by an Instruction 54. D3g: Log, Cent Proc; FIG. 107

A signal which issues when a particular situation exists during interrogation by an Instruction 54. Dec: FF, Sort Con; FIG. 185

The l-output signals of a control flip-flop which, when set to the l-state, indicates that a character has been read from a document and recognized by the Character Reader. Dec-Dec9, Dec-s5: Log, Sort Con; FIG. 187

The signals delivered by the Sorter Control Unit to the Sorter, which represent respectively the Sorter pocket into which a document is to be inserted. Dar: Log, Sort Con; FIG. 187

A signal which issues when a numeral on a document has been read and recognized by the Character Reader. DRCO-DRC19: Mem; FIG. 12]

The respective output signals of the 20 address drivers of the Memory. Dsyl, Dsy2: FF, Read-But; FIG. 176

The l-output signals of two control flip-flops which aid in retiming the data bits received by the Read Buffer from magnetic tape. Dt: FF, Cent Proc; FIG.

The l-output signal of a control flip-flop which, when set to the l-state, indicates that a programmed instruction has not been executed because a system component was busy or was not prepared. Efp: FF, P-Buf; FIG. 132

The l-output signal of a full alarm flip-flop which is set to the i-state if a parity error has been detected in data in the P-Butfer. E0224: Log, Cent Proc; FIG. 107

A signal which issues during execution of an Instruction 24 to reset the M03 flip-flop for indicating that the P-register is empty following the execution of the instruction. Em59: Log, Cent Proc; FIG. 107

A signal which issues during execution of an Instruction 59 for setting the P-Buffer mode control flip-flops to direct the execution of the selected operation. Em74: Log, Cent Proc; FIG. 107

A signal which issues during execution of an Instruction 74 to initiate transfer of a word from Memory to the P-Bufler. End: Log, Cent Proc; FIG. 107

A signal which issues during the last clock period in the execution of an instruction. Eoc: FF, Read-But; FIG. 107

The l-output signal of a control flip'fiop which, when set to the l-state, signals that the end of the line of data has been read by the Character Reader. Eod: FF, P-Buf; FIG. 133

The l-output signal of a control flip-flop which, when set to the l-state, indicates the conclusion of a P-Buifer operation, in order to provide proper delay for the Control Typewriter mechanism to return to its idle state. Eos: Log, P-Buf; FIG. 138

A signal which issues to indicate that a P-Butfer operation has been completed. Err: Log, Sort Con; FIG. 187

A signal which issues when the waveshape obtained from an improper character has been transmitted to the Character Reader, or when the Character Reader cannot recognize the waveshape received thereby. Ers: FF, Read-Buf; FIG. 174

The l-output signal of a sub-alarm flip-flop which is set to the l-state: if a row or column parity error is detected in a data word received by the Read Buffer from magnetic tape; if the Read Buffer has not been unloaded when the next word is received from magnetic tape or from the Character Reader; or if no data is transmitted into the Read Buffer from a tape block. Ersd: Log, Cent Proc; FIG. 107

A signal which eifects the resetting of the Ers flipfiop when the state thereof is interrogated by execution of an Instruction 54. Err: Log, Cent Proc; FIG. 107

A signal which issues during execution of an Instruction 67 to initiate the erasing of block markers and the backing of an identified magnetic tape. 

